In Rolland Best's PLL book, chapter 3.4.3, he stated that if the PLL used EXOR as the phase detector, the reference feed through will modulate the VCO output when divider N=3.
The modulated frequency component will be N*Fref +/- 2Fref and N*Fref +/- 4Fref.
My question is that why there is compenent located at N*Fref +/- 4Fref?
( i guess analog board is a wrong place to post it. )
I think the answer is that XOR gates make poor phase detectors. Modern charge pump phase detectors have an almost zero output spike when the PLL is locked. That spike is easily filtered with a simple RC lowpass filter.
'
XOR gates acting as phase detectors have a 50% duty square wave out (0 to +5Volt swing) when the PLL is locked. THAT is a huge amount of energy at the reference, and being a square wave has lots of odd harmonics in it. Probably 30 dB harder to filter out.