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type declarations in vhdl

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Bustigo

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How differ in use , in synthesize in debugging or in anything

type matrix IS array (0 to 3) of std_logic_vector (7 downto 0);

&

type row is array (7 downto 0) of std_logic;
type matrix is array (0 to 3) of row;
 

TrickyDicky

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The big problem is everything that works with std_logic_vector now will not work with row. Difining your own array type of std_logic is generally a bad idea. But from a logic point of view there is no difference.
 

TrickyDicky

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but thats the point. Std_logic_vector already exists, so why re-declare it. It makes your new type incompatible with other std_logic_vectors.
 

TonyM

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vhdl is a strongly-typed language and the point of that is to reduce errors. In this case, it stops you connecting your signals of different types together.

There's nothing bad about using your own type of std logic array. It''s good if you want an error indicated if you accidentally connect it to a std logic vector. That's the protection what strong typing gives you.

But if you want a design you can connect to other blocks and easy for others to work on, stay std_logic_vector.
 

TonyM

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You're welcome, glad to help :)
 
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