TX/PLL spur debugging at board level

[aaron_do]

Hi all,


I am working on an RF transmitter board with an on-chip PLL and TX. I did not design the chip, and the data sheet is extremely sketchy on the details inside. Unfortunately, the TX output shows a spur at approximately 1.33x the output channel frequency, and the amplitude is independent of the signal level (actually if I back off the TX power by 20 dB, the spur level drops, but above that it is fairly constant).

My question is, what would be a good technique to isolate the source of the problem. I am thinking it is likely to be a supply/grounding issue. I can probe the supply caps for the TX or the PLL, and if absolutely necessary, I could probably change some of the capacitor values here and there. I have tried probing the PLL supply caps hoping that the small disturbance of the probe would cause a change in the spur level, but so far no luck.

Any suggestion is appreciated. BTW, as we are working on small quantities, its unlikely that the chip manufacturer will give us much support.


thanks,
Aaron

 

[BigBoss]

Spurs come generally reference clock leaks/couplings from <somewhere> and poor ground connections are also their reasons.Especially ground connections of the Charge Pump of the PLL are very disturbing when they are shared with VCO or other forward elements' grounds.
What is your TX and Reference Signal frequency?

 

[biff44]

is there a corresponding spur at 0.67X the output frequency? it is possibly a modulation sideband.

IF you tune the output frequency, does the spur move to stay at 1.33X the output frequency, or does it stay fixed in frequency as the output is tuned? you need to do lots of little experiments like this to see where the spur is coming from.

 

[dick_freebird]

Is the block diagram detailed enough to show you clock
generation, intermediate tones and multiplied / divided
products? 4/3 would seem like an unusual ratio, wanting
a /3 somewhere and a 4X in the PLL.

You might find more in the time domain than the frequency
domain when hunting spurs. Particularly if you can find the
pins where this 4/3 tone is strongest, you may be able to
see a predecessor clock time-aligned with the spur artifact
(which might manifest as a square, or impulse) and deduce
the chain that creates it.

It might be useful to vary TX carrier independent of other
clocks, and confirm that the relation is always 1.33X, and
that this isn't just coincidental frequency-plan chest bumping
rather than a mixing or frequency product from the TX clock
creation. I have personally seen a thing like the 27th harmonic
of the 50MHz-ish PLL reference clock, times two for each edge,
step right onto a desired receive band. The relation may be
one you'd not even consider, but hard switching digital can
make a lot of on chip interferers at very, very high harmonic
numbers. Coupling can be longitudinal currents in supply
busses, magnetic, as easily as it can be electrostatic (voltage
coupling).

So you might just want to take a look at the very high precision
spur frequency and see if any of the known digital clock
derivatives / products, have an odd or 2*odd harmonic that
is dead-nuts.

 

[aaron_do]

Hello all,


thanks for all the replies. Before I address the replies, just a little background info since I guess I wasn't clear enough. The chip I'm working on is a full transceiver from MAC all the way to RF out. The datasheet doesn't give any details about what's inside, but I know roughly what's inside based on the application. My guess is that the prescaler is a /3 and it is mixing with the fundamental and somehow finding its way off chip (assuming a direct conversion TX).

Spurs come generally reference clock leaks/couplings from <somewhere> and poor ground connections are also their reasons.Especially ground connections of the Charge Pump of the PLL are very disturbing when they are shared with VCO or other forward elements' grounds.
What is your TX and Reference Signal frequency?

I reviewed the PCB design, and there is a nice big ground plane directly beneath the chip with a few vias going through it but not much else. At the bottom layer, there is another ground plane where all the decoupling caps are connected. However, the bottom ground plane is a little broken up due to other signal routing. I need to do a little investigation to find out what the other signals are...The reference frequency is 40 MHz, and the TX frequency is in the 5 GHz band with the spur at 1.33x of that.

is there a corresponding spur at 0.67X the output frequency? it is possibly a modulation sideband.

IF you tune the output frequency, does the spur move to stay at 1.33X the output frequency, or does it stay fixed in frequency as the output is tuned? you need to do lots of little experiments like this to see where the spur is coming from.

There is no 0.67x spur, but anyway, as I mentioned, the 1.33x spur is more or less independent of TX amplitude, so I doubt its a sideband. Its more likely either a direct leakage through the transmit chain from the PLL, or grounding/supply leakage. I somewhat doubt it is going through the transmit chain as the chip manufacturer is very reputable, and would be unlikely to make a mistake like that. Its more likely a board issue.

I've been doing some experiments as you say, but I would like opinions on other things I could try. I was thinking to maybe get a wire and solder a capacitor in the middle, and probe the supply decoupling caps. Problem is the probe would be an inductor at that frequency. I could also try and simply change the supply decoupling caps, but that will be a last resort.

Is the block diagram detailed enough to show you clock generation, intermediate tones and multiplied / divided products? 4/3 would seem like an unusual ratio, wanting a /3 somewhere and a 4X in the PLL.

Unfortunately, no details, but as I mentioned above, it could be a /3 prescaler mixing with the fundamental (assuming this is a direct conversion chip). There are probably a million other ways to get 4/3 though...

You might find more in the time domain than the frequency domain when hunting spurs. Particularly if you can find the pins where this 4/3 tone is strongest, you may be able to see a predecessor clock time-aligned with the spur artifact (which might manifest as a square, or impulse) and deduce
the chain that creates it.

I did a zero span check on the spur, and it is continuous. I guess that means that it isn't some kind of supply ringing, its really a mixed up tone. I have tried probing PLL decoupling caps, but I can't see any tones at all. Its probably because my probe is no more than a piece of wire I think I might need to redesign my probe.

It might be useful to vary TX carrier independent of other clocks, and confirm that the relation is always 1.33X

I will double-check that, but as I recall, I have tried several different channels, and 1.33x is consistent.

Coupling can be longitudinal currents in supply busses, magnetic, as easily as it can be electrostatic (voltage coupling).

I will look into that. Thanks.


Thanks for all the suggestions, any further hints are welcome. I suppose at this point its a matter of redesigning my board probe (its a little ugly at the moment), looking at the supply or biasing traces, and perhaps trying to change a few cap values.


thanks,
Aaron