two test case clock gating check circuit & clock divide generation circiut

Status
Not open for further replies.

kumarprakash1980

Newbie level 1
Joined
Mar 13, 2020
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
7
Hi all
I want two test case in verilog netlist and sdc to test the same
1)clock gating check circuit
2)clock divide generation circiut

prakash
 

Write your RTL, define the constraints (SDC) and then generate the netlist.............

show us what you have done, where you are stuck or ask if you have a specific question!
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…