Mar 13, 2020 #1 K kumarprakash1980 Newbie level 1 Joined Mar 13, 2020 Messages 1 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 7 Hi all I want two test case in verilog netlist and sdc to test the same 1)clock gating check circuit 2)clock divide generation circiut prakash
Hi all I want two test case in verilog netlist and sdc to test the same 1)clock gating check circuit 2)clock divide generation circiut prakash
Mar 13, 2020 #2 dpaul Advanced Member level 5 Joined Jan 16, 2008 Messages 1,799 Helped 317 Reputation 635 Reaction score 342 Trophy points 1,373 Location Germany Activity points 13,071 Write your RTL, define the constraints (SDC) and then generate the netlist............. show us what you have done, where you are stuck or ask if you have a specific question!
Write your RTL, define the constraints (SDC) and then generate the netlist............. show us what you have done, where you are stuck or ask if you have a specific question!