Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Two submodule with the same clock period, but with different root clock

Status
Not open for further replies.

qaz60402

Newbie level 1
Joined
Sep 27, 2015
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
12
In some designs, I notice that they have the same clock period, and with the same clock source ( PLL, for example ), but some submodules in this design use "different clock", which means that the source clock drives different clock root for these submodules, and makes the communication between submodules asynchronize.

It makes me confuse...Why do we have to do this?

Thanks.
 

dpaul

Advanced Member level 5
Joined
Jan 16, 2008
Messages
1,559
Helped
310
Reputation
620
Reaction score
310
Trophy points
1,373
Location
Germany
Activity points
11,556
keep in mind to check the phase of the two clocks.
 

harpv

Member level 4
Joined
May 30, 2012
Messages
71
Helped
19
Reputation
38
Reaction score
20
Trophy points
1,288
Activity points
1,823
One requirement could be to go easy on the clock tree.

By making the two clocks asynchronous you are telling the CTS tool that these clocks needn't be balanced, that means the skew can be different for the two clocks. So when doing CTS, the tool will not insert additional buffers to balance the two clocks. This saves area and gives more freedom to the tool to meet the timing for more critical paths.

This is mostly the case when you have modules running using same clock source but has very little communication between them.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top