two stage ota design problem.

[vhdl00]

I was trying design a two stage ota, the second stage was using a input common source nmos and a pmos current source load. Once I fixed the size fo the pmos. the input device Nmos is very sensive to the size, I mean a little bit deviation of size will drive the nmos to linear region?--which I don't think a robust design.
any suggestions?

 

[hoonsk]

If you are working in open-loop condition, to min the offset, the input NMOS has to be scaled with the previous stage NMOS current mirror (W/L) according to the current density, assuming you have a PMOS input pair.

 

[vhdl00]

thanks for your response. you are right. I just mean the input nmos size range(in saturation region) is very small, it is very possible in linear region considering 10%-30% deviation.

thanks again.

 

[hoonsk]

First, with feedback, it will take care of the biasing.
2nd, we layout the input NMOS to match with the previous stage NMOS current mirror such that the deviation won't be 30% but <2% with respect to each other.

thanks for your response. you are right. I just mean the input nmos size range(in saturation region) is very small, it is very possible in linear region considering 10%-30% deviation.

thanks again.

 

[vhdl00]

I was doing parameter analysis, setting the width of driver nmos of second stage as the parameter, doing dc sweep in cadence, there is really no much margin for the size. I mean sometimes, the size has to be exact to make sure the device in sat region. that's why I was worrying that it might cause problems consider the process variations. I was using ami06, minimum length.

thanks

 

[allan_guo]

Just set the ratio of pmos(2stage)/pmos(1stage)=nmos(2stage)/2*nmos(1stage)
it may work.I think the range may almost be rail-to-rail.