Two Stage amplifier design in 130nm CMOS Technology

[electronics20]

Dear all,
I need to design a two stage amplifier design whose characteristics are as follows in 0.13 TSMC technology.
The schematic is attached to this massage. I would be grateful if you could guide me.
Thanks

DC gain>= 70 dB
Unity gain band width>= 65 MHz
Power<= 150 uw
Slew rate >= 45 v/us
Output swing >=1 v

 

[erikl]

In Binkley's book Tradeoffs and Optimization in Analog CMOS Design, chap. 5 you can find 3 optimization examples for such an amp (OTA) for 3 different bandwidths/DC gains/slew rates, incl. W/L calculation and full characterization, for 0.5µm process, however. I think this could be helpful anyway.