Two sdc files and one design

[FRED_RIC]

Hi friends,

My name is Fred, I am electronics student and beginner in place and route field.

One of the inputs of place and route is the timing constraints (sdc file).

In our mini project there are two sdc files:
1) Pre cts SDC file
2) Post cts SDC file

Can someone explain me why is the reason to make to two files and not use just constraint file.

I attached the files to one zip file in comparing to each other (the left is pre cts, on the right hand post cts) and changes are marked.

Thanks,

Fred.

 

[skyismylimit]

The basic difference comes from the fact that after CTS, you need to remove some of the attributes with which you have modelled the clock (like transition, latency etc) and allow the tool to propagate the clock from the port/pin.

You are effectively doing this by over writting the old constraint with the new one.. instead you can hold the old constraint and append it with some remove_clock_latency commad and set_propgated_clock command.... it should also work..