Two question about LNA design

[lordfire]

1 In Thoms LEE's book , he suggests a inductively source degenerated LNA to minimum the noise figure, when he get a equation of input impedance including Cgs consideration whereas omitting Cgd, why Cgd is omitted, is it far smaller than Cgs in some simulation, Cgd is in the same quantity as Cgs, especailly in CMOS technology.

2 In IEEE ISSCC 2002, a paper is called Noise Cancelling in Wideband CMOS LNAs is submited, author is F. Bruccoleri, Klumperink , Nauta, they suggest a technology to cancel the noise to minimum NF, The LNA operats at the frequency between 2 to 1600MHz, NF is 2 dB.
I want to know How random thermal noise and flicker noise can be canceled in time region and frequency region, thanks

 

[flatulent]

The inductive source idea goes back to the days of valves/tubes. It is mentioned in the MIT RADLAB series of books from the 1939-1945 war.

I once saw a HP (now Agilent) application note where they had a strip from the source pad and was parallel to the ground layer on the top. They said to put a short between them at a point found experimentally by looking at the gain and avoiding a peak at the high frequency end.

 

[Mazz]

Usually for LNA cascode configuration is used also to avoid the negative effects of Cgd, so you can cosider it negligible.
I hope it can help.
Mazz

 

[cmosbjt]

Yes, Cgd is less than Cgs when the transistor is in saturation region. So Cgd is often neglected in small signal analysis. You can find the answer in some CMOS anlaog IC design books.

 

[DonJ]

Cgd and Cgs affect different circuit performance:
Cgd: Reverse isolation (Miller)

 

[sgperzoid]

1 In Thoms LEE's book , he suggests a inductively source degenerated LNA to minimum the noise figure, when he get a equation of input impedance including Cgs consideration whereas omitting Cgd, why Cgd is omitted, is it far smaller than Cgs in some simulation, Cgd is in the same quantity as Cgs, especailly in CMOS technology.

2 In IEEE ISSCC 2002, a paper is called Noise Cancelling in Wideband CMOS LNAs is submited, author is F. Bruccoleri, Klumperink , Nauta, they suggest a technology to cancel the noise to minimum NF, The LNA operats at the frequency between 2 to 1600MHz, NF is 2 dB.
I want to know How random thermal noise and flicker noise can be canceled in time region and frequency region, thanks

the inductive source degenerated LNA is probably the best architecture for CMOS narrowband LNAs, it offer the best noise performance, however, please be noted that the expression given in Thomas Lee's book and paper is slightly wrong, the correlation coefficient should ne minus in his current flow direction definition, while a Q is missed in his derivation.
the Cgd is neglected here due to the fact that a cascode MOSFET is used in the circuit to mitigate the Miller effect, it is a good approximation at relatively low frequency.

About the second paper, I also have some doubt on that, I dunt quite understand the cancling mechanism.

You may email to sgperzoid@tom.com if you would like to further discuss with me.

ThankS!

 

[dsjomo]

(1) Cgd is not negliable under GHz operation while the drain or collector is connected to high impedance or under high gain operation. But for MF and HF range, Cgd is negliable. The famous cascode amp. which lowers the Miller cap takes the benefit of the low input impedance of CG stage. If you match the interface between CS and CG stages (namely, treated as 2-stage amp.), the impact of Cgd grows again. Besides, the more you degenerate at source or emitter, the less the impact of Cgd or Cbc.

(2) About the noise cancelling, look at the path Y-> X -> GND, it's a votage divider, so for noise voltage resulted from drain noise current , the VnoiseY and VnoiseX are in the same phase with a ratio relationship (assuming that the buffer and adder have high input impedances). But for source signal Vs, Vx and Vy are in 180° phase difference. That's why the technique can cancel the noise and amplify the signal at the same time.

But , why can we ignore the noise of buffer and adder, huh? Though the noise of buffer could be cancelled in the similar way to the above. We need further equation based explanation of this circuit.

(3) There has been a long quarrel on MOS noise modelling. The gate noise is considered to be a result of Non-quasistatic operation. The problem is that, how do you measure or extract the alpha, delta and gamma values of your process and how do you know it is correct?? So, this model is only for education, and, a good problem for midterm or final exam . Some model engineer develop a new model, they segmentation the MOS (cut it into smaller pieces) and serial them. What does it mean? The segmentation is to simulate the gate delay. Under high frequency operation, the phase of gm is not zero, namely there is a time delay while you try to invert the channel beneath the thin oxide. This model is good for simulation, but abviously no good for education.

 

[dot13]

I also doubt about the noise cancelling method, in JSSC Feb, 2004, the authors published the new research circuit, while i just don't know why he didn't mention the load, without load, how can some S-parameters measured? While if a 50 ohm load added, the match will break.

The noise of the buffer and adder can be ignored by some circuit consideration. You may consult JSSC 2004, P. 275

 

[alitavakol]

because the feedback is small from the output and can be neglected

 

[stober]

I have tried one approch Bruccoleri introduced in Generating all Two-Mos-transistor Amplifiers leads to new wide-band LNAs. It is possibe to cancell the noise contributed by rf input transistor. But however, noise from transistor load is significant. Though we can obtain a little low NF from this circuit, but if we want to obtain higher gain, 20dB for example, a succeeding amplifier is recommended in his Doc. thesis. This is seriously deteriorate the NF, which makes this circuit uncompetitive.

 

[nikremt]

Though we can obtain a little low NF from this circuit, but if we want to obtain higher gain, 20dB for example, a succeeding amplifier is recommended in his Doc. thesis. This is seriously deteriorate the NF, which makes this circuit uncompetitive.

Why not keep "stringing" togther several "noise canceling" stages? Why do you have to follow the noise canceling stage with a stage that is not optimized for noise performance? If you can get 2dB NF and 10dB gain out of one stage using the noise canceling scheme, then just tack another one on the end of the first stage. Then you get 20dB of gain and a noise figure of about 2.2dB. I wouldn't call that "uncompetitive" as you did.

 

[Julian18]

I also doubt about the noise cancelling method, in JSSC Feb, 2004, the authors published the new research circuit, while i just don't know why he didn't mention the load, without load, how can some S-parameters measured? While if a 50 ohm load added, the match will break.

The noise of the buffer and adder can be ignored by some circuit consideration. You may consult JSSC 2004, P. 275

I read this paper, in the final implementation(Fig.6.), the authers use another current mirror at the output to increase the current flowing thru M2a and M2b. I guess the purpose of doing this is to increase the gm of these transistors to get low noise contribution. Well, how to deal with the noise generated from the source follower? furthermore, how to deal with the noise owing to the second current mirror at the output???I can not find any answer in their paper? any suggestions?

 

[Julian18]

also , how does this method deal with the induced gate noise??