(1) Cgd is not negliable under GHz operation while the drain or collector is connected to high impedance or under high gain operation. But for MF and HF range, Cgd is negliable. The famous cascode amp. which lowers the Miller cap takes the benefit of the low input impedance of CG stage. If you match the interface between CS and CG stages (namely, treated as 2-stage amp.), the impact of Cgd grows again. Besides, the more you degenerate at source or emitter, the less the impact of Cgd or Cbc.
(2) About the noise cancelling, look at the path Y-> X -> GND, it's a votage divider, so for noise voltage resulted from drain noise current , the VnoiseY and VnoiseX are in the same phase with a ratio relationship (assuming that the buffer and adder have high input impedances). But for source signal Vs, Vx and Vy are in 180° phase difference. That's why the technique can cancel the noise and amplify the signal at the same time.
But , why can we ignore the noise of buffer and adder, huh? Though the noise of buffer could be cancelled in the similar way to the above. We need further equation based explanation of this circuit.
(3) There has been a long quarrel on MOS noise modelling. The gate noise is considered to be a result of Non-quasistatic operation. The problem is that, how do you measure or extract the alpha, delta and gamma values of your process and how do you know it is correct?? So, this model is only for education, and, a good problem for midterm or final exam
. Some model engineer develop a new model, they segmentation the MOS (cut it into smaller pieces) and serial them. What does it mean? The segmentation is to simulate the gate delay. Under high frequency operation, the phase of gm is not zero, namely there is a time delay while you try to invert the channel beneath the thin oxide. This model is good for simulation, but abviously no good for education.