two dimentional matching array in layout design

[Junus2012]

Hello,

I am wondering why ABBA (also written as ABBA/BAAB) is preferable or used over ABAB , I see the second one has better dispersion
BAAB BABA

Secondly, I opened the IP cells from my foundry and I have seen that they only use two dimensional (also called cross coupled) for the differential pair transistors, and the rest of the circuit is layouted using simple one dimensional common centroid or interdegitized array.

I have noticed from the results I obtained in my work, that although having two diamentional array gives better matching, but increase the parastatic and degrades the dynamic performance of the circuit due to the complexity of wire routing

I would like to discuss with you on this

thank you in advance

best regards

 

[lazybear]

For ABBA or ABAB placement, personally I will refer ABAB considering all factors, including SA/SB. For better matching, 2 or more dimension will be referred.
Why people uses ABBA, I guess it could relate to an old document of TI about matching and common centroid. In that document, ABBA is common centroid and symmetry, while ABAB is asymmetry. So it might become convention for along while, just my guess ^_^

About the simple dimension you've mentioned, I think it's mostly related to operating freq. High speed design will refer simple matching structures.

 

[Dominik Przyborowski]

Layout techniques are used to supreme systematic mismatch effects. Check 3rd chapter of this work

 

[Junus2012]

Layout techniques are used to supreme systematic mismatch effects. Check 3rd chapter

Dear Dominik,
Thank you for your reply,

That is absolutely needed, but my question was different

I have done mistake in the post, I wrote the array in two diamentional but presented in one row and made my question fuzzy, below I am repeating the first queston from the former post



I am wondering why the two dimensional matched array transistors ABBA/BAAB is preferable over ABAB/BABA , I see the second one has better dispersion

thanks

 

[Dominik Przyborowski]

The answer is in the linked document.
ABBA is used to compensate linear gradient of process parameters (doping, Oxide thickness, etc.)

 

[Junus2012]

Dear Dominik,

sure I understand the purpose of matching, but I want to compare between those array, why figure a is mostly used while i see the matching in fig 2 is better

 

[Dominik Przyborowski]

You are not following response. Linear gradient. Look on attached document or at least write a line with none zero slope over both patterns and think.

--- Updated Mar 23, 2021 ---

impact of linear gradient of any parameter on marched pair performance:

--- Updated Mar 23, 2021 ---

edit: sthing was skrewed with image

 

[Junus2012]

impact of linear gradient of any parameter on marched pair performance:

Dear Dominik,
That is exactly useful picture expressing the things that I couldnt present, using this picture you will find that A=0%, B =0% of variation for both arrays in my former post (fig a & b ), and it is the main question for me, both of them provide same level of offset average, but fig.a is alwys being used rather than two, while for me I would say that b is practically should be better because the array has more dispersion.

 

[Dominik Przyborowski]

I didn't found your question is about 2D structure.
Regarding your patterns - they are identical. Check radial symetry vs center as origin.

 

[Junus2012]

I didn't found your question is about 2D structure.
Regarding your patterns - they are identical. Check radial symetry vs center as origin.

Yes it was a mistake of typing, in the first post I wrote in two dimensional form but it was coming like one line,

For me I do this stratigy whenever I want to test the array, I join line between each element to creat closed polegone, then I will have the center of it, the same I do with other array elements where all must have the same center.

can you please comment on my other questions in the first post

Thank you once again
Regards

 

[timof]

Note that systematic mismatch may be caused not only by "gradient" or process effects, but also - by layout parasitics effects, parasitics mismatches - where effective series resistances, or coupling capacitances, or RC delays may get mismatched because of the asymmetries of the layout.

Typical effects like that include current sources mismatch due to mismatch in voltage drop (metal debiasing) on the ground net (and hence Vgs and Ids mismatch), or capacitance mismatch in binary weighted capacitor arrays (SAR ADC), etc.