TSPC latch delay time

[Engineer4ever]

Hi,

I am designing a Serializer and the last stage requires a high-speed architecture so I used TSPC topology for flip-flops and latches. The problem is I need the TSPC latch to delay its input signal by half a period and I tried everything but the delay is still about quarter a period. Is there any solution for that problem or is it common that TSPC latch works like that?

Thanks in advance,

 

[erikl]

Even a TSPC latch has some propagation delay (from CLK to output), so this might well be a quarter of your period?