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TSPC DFF post layout simulation

bjihoon

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I designed conventional TSPC DFF circuit and I aplplied the ideal 4 phase clock(0, 90, 180, 270) to each DFF's clock port like below. (each circuits in the white boxes are same except for input signal.)
1674207791665.jpeg

1674208975249.png
I used this DFF circuit. It is for NRZ to RZ data converting.
And I did post layout simulation. but result is something wrong.

1674206886741.png
1674206906462.png

left(above) is schematic simulation and right(below) is post layout simulation. the output was strange.

At first, I thought it's due to parastic cap. So I did everything I could.(using another DFF, changing layout)
But when I used another DFF, the result is almost same.

And I tried one block like below.

1674207392515.png


In this case, post layout simulation result is almost perfect for each 4 phase clock(0,90,180,270). So I thought it isn't due to parastic cap in layout.

1674208249894.png
1674208335896.png

left(above) is one block. And right is total block. In right(below) layout, each block is totally same with left(above) one block. (4 blocks in right have each 4 phase clock.)

In summary, the post layout simulation result was almost perfect when the clock signal was different(0, 90, 180, 270) in one block. But when I simulated in total block, the results were strange.
So I didn't think it is due to parastic cap.
Why does this happen? help me, please.

Additionally, I added a label in layout to see the signal at each point of the circuit. And I did post layout simulation but the results were more strange. I just added the label to layout, but did the result get weird?

please help me. I want to solve this problem. I think this is related to cadence, PEX setting.

1674207634950.png
 
Last edited:
Solution
If you look at the graphs, it seems as if bit 1 comes correct, bit 4 should be in the other order
1 -> 1
2 -> 3
3 -> 4
4 -> 2
5 -> 5
6 -> 7
7 -> 8
8 -> 6

The pattern is the same. Are the labels on their right position in the layout such that the tool knows it's simulating the right ports.

What does the netlist say? Check the input.scs.

jjx

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This is perhaps a bit naive question, but haven't you just swapped pins in the layout or so. (that might explain the label issue too).

One tip could be to look at the netlist that PEX generates, or the spectre netlist that you simulate.
 

bjihoon

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This is perhaps a bit naive question, but haven't you just swapped pins in the layout or so. (that might explain the label issue too).

One tip could be to look at the netlist that PEX generates, or the spectre netlist that you simulate.
Can you explain it in more detail?
I don't understand "swapped pins"
Thank you for your response.
 

jjx

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If you look at the graphs, it seems as if bit 1 comes correct, bit 4 should be in the other order
1 -> 1
2 -> 3
3 -> 4
4 -> 2
5 -> 5
6 -> 7
7 -> 8
8 -> 6

The pattern is the same. Are the labels on their right position in the layout such that the tool knows it's simulating the right ports.

What does the netlist say? Check the input.scs.
 
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    bjihoon

    Points: 2
    Thank you for your help. Thanks to you, I was able to solve it.
Solution

bjihoon

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If you look at the graphs, it seems as if bit 1 comes correct, bit 4 should be in the other order
1 -> 1
2 -> 3
3 -> 4
4 -> 2
5 -> 5
6 -> 7
7 -> 8
8 -> 6

The pattern is the same. Are the labels on their right position in the layout such that the tool knows it's simulating the right ports.

What does the netlist say? Check the input.scs.
Wow.. you're right! Thank you for your help.
Input clock signals were misdirected.
Thanks to you, I was able to solve it.
 

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