TSMC MIM capacitor array layout problem

[guow06]

I am using TSMC 90nm technology to design a SAR ADC. A capacitor array 18x10( with unit cap 3x3) is created in my layout, but since there is a CTMDMY layer around the capacitor, a DRC violation about density exists. I can not fix the violation. Is there any way to fix that?

 

[hanif]

Hi,

check these links

https://www.edaboard.com/threads/192805/

https://www.edaboard.com/threads/216061/

 

[leo_o2]

Metal density is too high or too low?

 

[nassim_el85]

As I know there is no relation between CTMDMY layar and Density error of DRC!!!

CTMDMY (capacitor top metal dummy layar) is a dummy layer to specify your capacitor area, which is useful in LVS process.
The density DRC error is an error which is occure when the density of a metal is less than a percent which is specified in the technology documents.

 

[guow06]

what the error show is : Min. density for CTMDMY area <=40,000 um2, {Mcap inside CTMDMY} density range over any 200umx200um area (checked by stepping in 100um increments) 50%. This rule is only applied to the overlapped area of checking window and CTMDMY >= 2500 um2.

---------- Post added at 21:41 ---------- Previous post was at 21:39 ----------

It is strange that TSMC 90nmLP (for low power), almost the same technology , does not have this problem.