TSMC 65nm DRC Violation - Seal Ring Related

[sincplicity]

I put a TSMC provided seal ring around a design which passes DRC but when I tile the design with the seal ring for the top level, I end up with 5 errors related to the seal ring. Any ideas on how to correct?

RV.W.1.WB
RV.S.3.1.WB
...

The check text for one

 

[ThisIsNotSam]

AP and RV errors in the sealring can be ignored. The DRC deck does not properly recognize the sealring.

Check the location of your violations. As long as they are not in the core area you are fine.

 

[sincplicity]

Thank you. That was the conclusion I was reaching. The violations are on the sealring itself. I even tried wrapping the top-level design in sealring with same errors.