TSMC 65nm capacitor crtmom

[Mounikap]

Hello everyone,

I am using TSMC 65nm. I wanted to use "crtmom" in my circuit. And it has 3 terminals. So anyone can you please let me know whether i need to connect the bulk to either ground(VSS) or power supply(VDD) ? I checked the PDK documents but didn't find information about the bulk connection.

 

[sidun.av]

Hi @Mounikap ,
1. Bulk terminal of crtmom does not affect the performance of the capacitor directly. It is a protective structure that serves as shielding from the substrate noise.
2. Basically, you can connect this terminal to any potential you like (whatever you think is quite and strong enough to provide proper shielding). Usually, the VDD or GND potential is used.
3. Before assigning a net to this terminal, double-check the layout option of this terminal (whether it is PWELL or NWELL). If it is NWELL, it would be better to connect it to VDD, if PWELL - to GND.

Hopefully, that helps.

 

[Mounikap]

Thank you for the information @sidun.av I have attached the capacitor layout diagram. Can you please tell me how can i check the layout option of the particular terminal ? Actually in the Layout i have placed the crtmom capacitor and checked the used metals so in that NW was there so am thinking this bulk should be connected to VDD. Is it correct process ? Can you please tell me how can i check the particular terminal whether it should be connected to NW or PW ?

 

[sidun.av]

It should be mentioned either in schematic or layout PCELL window (when you open Instance properties, or pressing Q). In your case your bulk is connected to NWELL, you can check this by disabling all layers in your layout editor and leaving only NWELL. So yes, your bulk terminal should be using VDD.

 

[Khan_001]

Hi @Mounikap ,
1. Bulk terminal of crtmom does not affect the performance of the capacitor directly. It is a protective structure that serves as shielding from the substrate noise.
2. Basically, you can connect this terminal to any potential you like (whatever you think is quite and strong enough to provide proper shielding). Usually, the VDD or GND potential is used.
3. Before assigning a net to this terminal, double-check the layout option of this terminal (whether it is PWELL or NWELL). If it is NWELL, it would be better to connect it to VDD, if PWELL - to GND.

Hopefully, that helps.

in my case I connected to GND...and in the layout I created a p-substract ring around the capacitor as a bulk connection , but when i run DRC it give me below error "MOM.R.1 @ poly shielding and underneath NW or PW must bias at same potential for reliability consideration"...do you know how to reslove it... Interesting point is LVS is clean

 

[sidun.av]

in my case I connected to GND...and in the layout I created a p-substract ring around the capacitor as a bulk connection , but when i run DRC it give me below error "MOM.R.1 @ poly shielding and underneath NW or PW must bias at same potential for reliability consideration"...do you know how to reslove it... Interesting point is LVS is clean

It's better to refer to the Design Guidelines document and check the explanations for the error.
I guess that you've connected your third terminal of MOM cap (poly shield) to VDD and then created a PWELL around it and connected to the ground.

Following what DRC tells, it should be done in two ways:
1. Your poly shield (3rd terminal) is connected to VDD, NWELL is connected to VDD;
2. Poly shield connected to ground, PWELL connected to ground.

I guess the reason for that is that by applying different potentials to the poly shield and WELL underneath it you create a parasitic capacitor which might affect the value of your MOM cap.
Hopefully, that helps.

 

[Khan_001]

It's better to refer to the Design Guidelines document and check the explanations for the error.
I guess that you've connected your third terminal of MOM cap (poly shield) to VDD and then created a PWELL around it and connected to the ground.

Following what DRC tells, it should be done in two ways:
1. Your poly shield (3rd terminal) is connected to VDD, NWELL is connected to VDD;
2. Poly shield connected to ground, PWELL connected to ground.

I guess the reason for that is that by applying different potentials to the poly shield and WELL underneath it you create a parasitic capacitor which might affect the value of your MOM cap.
Hopefully, that helps.

Thank you so much, bro. Now I got the point. The issue was in the default configuration of crtcom. By default, it is set to N-well, and in the schematic, I connected the bulk to VSS. So in the layout, I changed the WellType from N to P and kept the substrate ring as it was. Now the issue has been resolved. By the way, is this the correct approach or not? Thanks once again!

 

[sidun.av]

Thank you so much, bro. Now I got the point. The issue was in the default configuration of crtcom. By default, it is set to N-well, and in the schematic, I connected the bulk to VSS. So in the layout, I changed the WellType from N to P and kept the substrate ring as it was. Now the issue has been resolved. By the way, is this the correct approach or not? Thanks once again!

As long as you are keeping both shield and WELL at the same potential, this is correct. So,
PWELL case: PWELL and shield are connected to VSS;
NWELL case: NWELL and shield connected to VDD (or any other strong potential).