Trying to use veriloga to write an edge detector

[foshanno1]

Hi,

So i am trying to use verilogA to write an edge detector. I can't think of a good way to do this. all i need is to trip the output whenever the input changes. I would have the cross function but the crossing threshold can change. so for example, if the input goes from 0V to 5V, I want to trip the output, but in the case when I go from -2V to -8V, I also want to trip the output. I am not sure how to do this since this requires me to keep recording the previous voltage and current voltage value? would I need a clock to do this ? Any help would appreciate it. Thanks

 

[KlausST]

Hi,

A design starts with requirements, a functional description, specifications.
Not only what and when it should work ... but also the limits where it should not react.
Noise comes to my mind.

Voltages, rise rates, timing....

A sketch with input signals and output signals and the according timing.


Klaus

 

[BradtheRad]

A capacitor differentiator (series capacitor) can convey a rapid change in voltage no matter what is the initial volt level.

 

[D.A.(Tony)Stewart]

Your spec should read something like
dV > x in duration dt < y or dV/dt > x/y

but if you also want dV < -x then you need two comparators and an OR gate logic.

What else do you want or don't want?

 

[dick_freebird]

If you have a deriv() function (and I'm prone to
assume so) then that would seem appropriate.
Amplify into clipping and put a known good
logic buffer on the back if you mean to use,
not just plot the output signal.

"Qualifying" the "edges" vs other noises /
interferers / aggressors will probably be more
of the work if you have non-ideal inputs.

 

[D.A.(Tony)Stewart]

The better choice might be to define the "release" voltage and current such as a 12V 20 mA relay goes to 0 mA or open circuit when released.

Then release thresholds could be >2.5 or < -5 using a dual comparator as a window detector.
Does that work for you?

 

[danadakk]

How to design a good Edge Detector - Surf-VHDL

The Edge Detector is a simple circuit that allows you to reveal the edge of an input digital signal. Here you can get the VHDL code of an edge detector

surf-vhdl.com

Designing Edge Detectors in Verilog and SystemVerilog

Learn how to design rising and falling edge detectors, as well as a both edge detector in Verilog and SystemVerilog. Achieve precise control over your signals and advanced functionality in digital circuits.

circuitcove.com

Proper way for signal edge detection in Verilog

I want to detect a rising edge of a signal from a flip-flop AA to BB +----+ A ----------------| |----- OUT +----+ | BB | B ----| |------|> | ...

stackoverflow.com

 

[D.A.(Tony)Stewart]

Hi,

So i am trying to use verilogA to write an edge detector. I can't think of a good way to do this. all i need is to trip the output whenever the input changes. I would have the cross function but the crossing threshold can change. so for example, if the input goes from 0V to 5V, I want to trip the output, but in the case when I go from -2V to -8V, I also want to trip the output. I am not sure how to do this since this requires me to keep recording the previous voltage and current voltage value? would I need a clock to do this ? Any help would appreciate it. Thanks

You can't define an edge detector unless you define state boundaries and absolute I/O levels.

You wanted +ve edge above 0 and -ve edge below 0 but this can be defined by levels alone.

You must start by a proper spec before implementation.

I did ask you to respond to a simple solution.
RSVP