Trying to understand saturation in a single switch Forward converter

[funberry]

I am coming from 60Hz line transformer design, and somewhat new to SMPS.

I am trying to understand something about core saturation.
In laminated line trafo, the closest you ever come to saturation is during idle operation - no load on secondary, just magnetizing current.

Any current drawn from secondary will cause an increase in primary current, but that reflected current does not bring the core any closer to saturation, as it does not contribute net flux density ( in fact it brings you farther from saturation, by increasing copper losses.)

Is it the same in a single switch forward converter? The magnetizing current is the only contributor to net flux density?

Assume an open loop, where you peg the DC to 49% , then draw ever increasing current from the secondary ( ignoring for a moment copper losses). A naive thought would be that the ever increasing reflected primary current is converted into added flux, but that added flux is converted into secondary current, so no net flux density increase.

I have read that excessive load transients can sometimes cause saturation, and that would confirm that my understanding ( above ) is wrong.

So, can a FWD converter core saturate from secondary load, or are magnetizing current and duty cycle the only culprits?

thank you kindly.

 

[mtwieg]

Is it the same in a single switch forward converter? The magnetizing current is the only contributor to net flux density?

Yes, magnetizing current alone is, by definition, what determines magnetizing flux.

I have read that excessive load transients can sometimes cause saturation, and that would confirm that my understanding ( above ) is wrong.

This can be the case if the transient forces the duty cycle too high. Part of the operating principle of the forward converter is that the magnetizing flux is brought back to zero during the switch's off period. This is accomplished by using the third energy recovery winding, which clamps to the input DC voltage while the switch is off and provides a path for the magnetizing (and leakage) currents to flow. Typically the energy recovery winding is has the same number of turns, and thus the same inductance as the primary winding, therefore so long as the duty cycle of the converter does not exceed 50%, the volt-time product applied the primary can always balance to zero. Therefore forward converters should be designed to operate below 50%, but if a large transient occurs then it may shoot too high and saturate. But a good design will have a hard limit on controller duty cycle, so this will never be allowed to happen (at the expense of poorer response to large transients).

 

[funberry]

So once you've properly designed for safe magnetizing current, and use a PWM that's internally limited in duty cycle, you never have to worry about transients destroying the circuit by saturation.
Although they could still destroy it otherwise. A hard transient, such as that created by flicking a mechanical switch to connect the full rated load, could still cause spikes that may exceed voltage specs of either the secondary diodes or the MOSFET and kill something.

I have killed several MOSFETS in experimenting with such a circuit. My test loading is very rudimentary , and consists of connecting a dummy power resistor by hand to the output, after the output has stabilized into a minimal baseline load.

Once the MOSFET blew by itself. Another time the secondary rectifiers blew (open), and not the switch. Still another time they all blew, (because one of the secondary rectifiers failed short, I suspect this may have happened first, which then took down the MOSFET afterwards.)
I know, now I have to start experimentally determining snubber circuits for the secondary rectifiers, and for the MOSFET to reduce spikes, and improve wiring to reduce ringing.

But in all of this I was still wondering if core saturation wasn't perhaps to blame at any point.

 

[mtwieg]

So once you've properly designed for safe magnetizing current, and use a PWM that's internally limited in duty cycle, you never have to worry about transients destroying the circuit by saturation.

Yes, though a rigorous design will also account for leakage inductance, remnant flux, etc to adjust the duty cycle limit to a little less than 50%.

Although they could still destroy it otherwise. A hard transient, such as that created by flicking a mechanical switch to connect the full rated load, could still cause spikes that may exceed voltage specs of either the secondary diodes or the MOSFET and kill something.

A sudden load transient doesn't necessarily have to damage anything. It depends on the control loop then. For example, cycle-by-cycle current limiting on the primary should prevent excessive stresses on devices during transients (and also helps prevent saturation).

I have killed several MOSFETS in experimenting with such a circuit. My test loading is very rudimentary , and consists of connecting a dummy power resistor by hand to the output, after the output has stabilized into a minimal baseline load.

Once the MOSFET blew by itself. Another time the secondary rectifiers blew (open), and not the switch. Still another time they all blew, (because one of the secondary rectifiers failed short, I suspect this may have happened first, which then took down the MOSFET afterwards.)
I know, now I have to start experimentally determining snubber circuits for the secondary rectifiers, and for the MOSFET to reduce spikes, and improve wiring to reduce ringing.

But in all of this I was still wondering if core saturation wasn't perhaps to blame at any point.

If saturation was the culprit then it should be apparent by examining the primary current waveforms for an abrupt change in di/dt (though this could be due to the output choke saturating as well).

 

[funberry]

Thank you kindly mtwieg.
It then means there is no saturation possible here, so spikes are the next suspect.

The volt seconds per turn are nowhere near saturation. ( 165V, 0.000006 s, 25 turns) ( ETD44, N87 ferrite ). I used triple-insulated wire and mingled the primary and secondary together to minimize leakege inductance. Leakage inductance is below the 3uH baseline of my meter.

I only have a 1980's analog scope, with no storage. I can view repetitive waveforms, and there is no indication of saturation in the drain current at either no load ( low load) or full load. I cannot view single-event transients, so I thought saturation might be occuring there.

There is no control loop (yet).
Because of my low comfort level with SMPS, I am approching this in a sepwise manner. First prove you can convert power, then add detail . My UC3845 runs at 80KHz, and is pegged at 49% DC by a potentiometer. ( and can't go over 50 anyhow.) The current limit is disabled because I want DC at 49% no matter what. This is just a proof of concept to test the maximum power limits of the design.

This converter is intended to put out 40VDC at 5A. It it hard wired into a 2K ohm minimal load resistor. Unloaded output is 98V. I then connect by hand a large 8 ohm test resistor. Half of the time it delivers 40V into the load reliably for 5 minutes, when I disconnect it because the load gets too hot.
The other half of the time, something blows the moment I connect the load. I understand that the way I connect my load is nasty. ( plus there is switch bounce with that).
I think my next step is to build an electronic test load: 4-5 power mosfets paralleled and bolted to a large heatsink, with gates driven from a variable voltage divider.

When the unit survives the step load and works, it emits audible swishing noise ( I believe from the transformer or output inductor ). At the same time, switching node waveforms show a subharminic oscillation. The waveform splits into 3-4 identical images, time shifted by about 20% of the wave period, and rapidly vibrating left and right. At low load, there is no noise, and waveform is clean, with just some ringing overshoot to remind me I 'll later have to revisit the layout.
If there had been a control loop, I might have suspected the subharmonic was caused by something in the loop, but that is out of the question here.

Best Regards

 

[mtwieg]

Thank you kindly mtwieg.
It then means there is no saturation possible here, so spikes are the next suspect.

The volt seconds per turn are nowhere near saturation. ( 165V, 0.000006 s, 25 turns) ( ETD44, N87 ferrite ). I used triple-insulated wire and mingled the primary and secondary together to minimize leakege inductance. Leakage inductance is below the 3uH baseline of my meter.

To clarify, limiting the duty cycle only prevents saturation due to flux walking (staircase saturation). Saturation can still occur within each PWM cycle if the volt-time product is excessive. From your numbers I calculate a flux swing of around 229mT. N87 saturates at >350mT, so it might seem like you're fine. However, when ungapped it also has remnant field of >150mT, so 229mT of swing may actually cause saturation (if you don't have enough air gap).

As for the audible noise and subharmonic oscillation, that should not occur unless you have a current mode controller. Can you post a schematic?

 

[funberry]

This is the schematic.

some part numbers are not right ( like the TIP3055 switch ) Eagle did not have templates for my MOSFET and some other parts, so I chose whatever component would give me the desired PCB patterns. For example All inductor pins are implemented as PADs, which I can re-position on the PCB for my final footprint.

The voltage feedback loop is not populated, and neither is the lower (negative) secondary side. The AUX supply is not populated, PWM is powered from isolated external 14V supply

All parts are thru-hole except where noted.

R1 82K
C1 470PF
R2 15K
C3 0.001
R5 0.36 OHM 2W SMD THICK FILM
R8 1K
C5 470
R6 10 OHM SMD THICK FILM
R3, R4 4.7K
R17 + OPTO REPLACED BY 1K POT
C2 1UF MLCC SURFACE MOUNT AT IC PINS
R9, R10 220K
D1 MUR260
D4 18V TRANSZORB
Q1 FCA22N60
D9, D10 MBR20H150




<a title="converter.jpg" href="http://obrazki.elektroda.pl/5557495300_1389291755.jpg"><img src="http://obrazki.elektroda.pl/5557495300_1389291755_thumb.jpg" alt="converter.jpg" /></a>

 

[mtwieg]

Okay so you are using current mode control. But even so subharmonic oscillation ideally can't occur in a forward converter limited to <50% duty cycle. However any delay in the current mode feedback loop (like your gate driver delay, and that lowpass filter to the sense pin) can cause instability at at lower duty cycles (on the other hand, the magnetizing current should supply some slope compensation to counteract this).

In any case you should do some open loop testing to track down the cause of the device failures and subharmonic oscillation. The primary side current limit should prevent excessive power dissipation, even during sharp transients and overload conditions. Your failures may be due to overvoltage if your leakage inductance is high.

oh, and I almost missed one important thing. You seem to be using an auxiliary winding to bootstrap the converter, but this is not normally done with a forward converter. Depending on its polarity with respect to the other windings, it can interfere severely with normal operation. Could you update the schematic to show the winding polarities?

 

[funberry]

The auxiliary winding is not used- it is open . power is currently supplied from an external isolated 12V supply.

This matter of remnant magnetization disturbs me though.
150mT is more than a third of total flux headroom. I thought the whole idea of soft ferrites is that they have negligible remnant magnetization. The area inside the BH loop is small because they have low coercivity. if you suggest such large remnant magnetization, that would imply there is a large area inside the BH loop, and therefore a very large energy loss. ( gapping would skew the loop, not change it area , no?)
It would mean that even with bipolar topologies -where the loop circumference is travelled completely, - the entire area inside the loop is energy lost as heat. It would mean that push-pull or full bridge tranformers would get very hot before any copper or eddy current losses . And those topologies are never gapped - as I understand.

I have looked at over a dozen forward converter reference designs yet never seen any mention of a core gap, or a specification of the size of such a gap, information that's always present in flyback designs.
What gives?

 

[mtwieg]

This matter of remnant magnetization disturbs me though.
150mT is more than a third of total flux headroom. I thought the whole idea of soft ferrites is that they have negligible remnant magnetization. The area inside the BH loop is small because they have low coercivity. if you suggest such large remnant magnetization, that would imply there is a large area inside the BH loop, and therefore a very large energy loss. ( gapping would skew the loop, not change it area , no?)
It would mean that even with bipolar topologies -where the loop circumference is travelled completely, - the entire area inside the loop is energy lost as heat. It would mean that push-pull or full bridge tranformers would get very hot before any copper or eddy current losses . And those topologies are never gapped - as I understand.

I believe you're correct that introducing an air gap does not change the area of the hysteresis loop for a given flux swing ΔB. However, the idea behind adding an air gap is that you will also add turns, which will reduce the ΔB and therefore core losses. It should be noted that usually in single ended forward converters, your transformer losses will normally be dominated by copper losses.

I have looked at over a dozen forward converter reference designs yet never seen any mention of a core gap, or a specification of the size of such a gap, information that's always present in flyback designs.
What gives?

It's not uncommon for forward transformers to have a very small air gap (we're talking a few thousands of an inch) to reduce Br. I rarely see it specified in schematics, but that's not surprising since most schematics just aren't detailed. Sometimes it's just a matter of using loose core clips to hold the pieces together, or wiping a pole a few times with sandpaper.

Have you actually probed primary current for any evidence of saturation?

 

[BradtheRad]

This converter is intended to put out 40VDC at 5A.

This works out to 200W continuous. Your 12V supply needs to provide 20 A avg. (Call it 22A with losses.)

Suppose your converter operates at 50% duty cycle and DCM. Then current peaks must be 55A or so.

To do all this, you must keep the 12V loop ohmic resistance below 0.22 ohm. If it is greater, then you may have to go into CCM and/or lengthen your duty cycle.

It's best not to attach your full load right away. Try a fraction of that while you are experimenting.

 

[funberry]

Actually , the 12V is the aux supply, which powers the pwm. I use external supply to eliminate the complexities of startup during raw testing.
Input to the SMPS is 120V line , or 165V link capacitor voltage.

 

[funberry]

It's not uncommon for forward transformers to have a very small air gap (we're talking a few thousands of an inch) to reduce Br. I rarely see it specified in schematics, but that's not surprising since most schematics just aren't detailed.

OK, so I'll add a thin sheet of paper between the core halves before assembling them.
That means there will be some stored energy. I figure I could recover that stored energy through the AUX winding, by using an opposite polarity AUX winding, like a flyback secondary. Now that I look at some forward converter schematics, I notice the AUX winding IS wound in opposite direction and is rectified like a flyback.

I also took apart the transformer from a Lambda forward SMPS, and managed to separate the core halves with solvent. There was some varnish accumulated between the core halves. I removed all the excess varnish with solvent and pushed the core back together. The primary inductance was 1mH before doing this . It was almost 4mH afterwards.

 

[BradtheRad]

Actually , the 12V is the aux supply, which powers the pwm. I use external supply to eliminate the complexities of startup during raw testing.
Input to the SMPS is 120V line , or 165V link capacitor voltage.

Sorry, my mistake. Guess I should have looked more closely at your post #5 line 3.

So instead your primary draws 3.5 amps (1 mH, 80 kHz, 165V). At switch-Off, my simulation shows high-voltage spikes approaching 1 kV across the primary. This appears at the collector of your switching transistor. Does your schematic contain any snubbing network?

The output diode (D9 I assume) carries 12 A peaks.

I am simulating a flyback topology with your specs. So my talk is just theoretical. I do not know if your forward converter has a waveform designed to eliminate the spikes.

I did find that high voltage spikes are a major obstacle, when I tried to build an inverter once upon a time.