trr of intrisic diode in FET?

[cupoftea]

Hi,
Do you know what is trr of the BSC027N04LS intrinsic diode?

BSC027N04LS

https://www.infineon.com/dgdl/BSC027N04LSG_rev1.04.pdf?folderId=db3a3043156fd5730115c7d50620107c&fileId=db3a30431689f4420116c4323646080c

Qrr is 45nC.
We are using it as a synchronous boost upper FET (5 TO 24V, 3.75Aout)
Two are in parallel.

 

[crutschow]

Do you know what is trr of the BSC027N04LS intrinsic diode?

That's not given in the data sheet so you would have to test the device to determine that.

 

[Easy peasy]

actually it is given if you read the data sheet carefully, Qrr = 45nC for 20V reverse applied and dif/dt of 400A/uS and starting at If = Is = 69 A ( i.e. lots of minority carriers in the junction )

400A/us is a sweep out rate of 0.4A / nS, over 30nS say the current will go from 0 to -12A, ( once the current reaches 0 from its forward level of 69A ) this is 180nC

since 180nC is quite a bit more than 45nC, it will be fair to assume the Trr will be in the order of 30nS or indeed even a bit less.

--- Updated Dec 2, 2022 ---

the capacitance as the current reverses is close to 3.2nF ( Vds = 0 ), to charge this to -20V requires a certain amount of charge / current that adds to that in sweeping out the minority carriers.

In this case, for our estimated 30nS, 400A/uS ( 400mA / nS ) at 12A peak ( 6A ave ) this would require < 64nC,

which is 2.13A over the 30nS, actually these figures will be lesser as the Cds falls quite a bit with rising volts.

So 30nS Trr under 400A/uS current slope might be pretty close to the mark.

Due to capacitance, much faster -dIf/dt will of course produce higher peak reverse currents, and harder snap off of the internal diode due to faster channel clearing of minority carriers. The harder snap off is ameliorated a little bit by the D-S capacitance ....

 

[dick_freebird]

Regardless of what the mfr may specify, if you expect to
light up the body diode then you ought to take your own
data at extreme hot conditions, past the current you will
claim to tolerate.

Good material quality is not necessarily your friend here,
the "best" silicon may be the worst for excess hang time.

30ns Trr is way, way below material lifetime for a high
voltage junction doping. There may be tricks like "getter
junctions" to extract charge by layout design. But you
aren't going to see a natural single PN junction that
recovers in 30ns even on a 40V (N 3-5 ohm-cm background)
diode. You need a means of elevating bulk recombination
(gold doping, etc.) or a "circuit approach" like shorted
P+/N+ regions whose smaller depletion region will "sweep"
carriers that diffuse into its influence and recombine them
in the highly doped, short lifetime "plug".

With normal dopings being in the 1E15 - 1E16 range for the
lighter doped side of the Ndrift / Pbody blocking junction, you
can see natural lifetime in the multi-microsecond range.

 

[Easy peasy]

It's only a 40V fet - within which - the diodes perform way better than for fets > 300V

Which is why they can be used at 400kHz in active rectifying sections in modern power supplies

 

[dick_freebird]

It's only a 40V fet - within which - the diodes perform way better than for fets > 300V

Which is why they can be used at 400kHz in active rectifying sections in modern power supplies

Even so, I used to work in a lot of 40V bipolar technologies
and I'd see storage times in the us range if I didn't play tricks
with layout (nobody wanted gold in the 4" fab after the 3" line
closed). In fact I got screwed by the modeling folks on that
aspect so many times (not to mention that one design guy who
reached into the shared models and crunk TR down until his
design passed prop delay, and didn't tell anyone, so we all
got a surprise), I ended up measuring for myself and refitting
the models for several of the subflows. And knowing the deal,
at 40V (w/ no Schottky), pushing some of those fast-recovery
device design styles onto the "approved device list" for the
process branch that -I- got to lead the development on.

Hence my "trust issues" and advice to measure your own,
like you mean to run it.

I was able to do 1MHz switching PWMs in that technology
familiy but the narrow pulse operation was tough to get
and never quite as good as the Unitrodes we were trying to
emulate; while JI sucks for some things, having a "getter"
the size of the whole collector tank sure does help out TR
in the NPNs. On dielectric isolation there's no place to go,
but the base (with its weak incoming drive); not like the stiff
VEE potential on a JI standard linear substrate. The power
FET is more similar to the DI case as it has no counter-doped
handle, drain / drift N- is all there is until you hit the die attach.

MOSFETs, being majority carrier devices, might be able to
use metallic doping to kill lifetime. Or neutron irradiation.
No idea, whether any do. It's (gold) still done in some corners
of the discrete power and signal transistor segment. But
doing it with layout alone lets you run at more fabs.

 

[Easy peasy]

As you say, metal gate Si mosfets can reverse the field in the channel very quickly leading to turn off times ( current fall times ) of < 25nS.

For the inherent diode, Pt and Au are used to speed these babies up - although the lighter doping is a huge advantage ( 40V )

dv/dt triggering ( hard diode turn off ) of the inherent NPN is almost a thing of the past too ...

which is why high speed / high current buck converters ( 400kHz with 20nS transition times ) are now quite common-place at these lower voltages ... and up to 10A per fet or more ...