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Trouble with relative propagation delay in Allegro v16.0 GXL

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jonpry

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I am trying to setup some constraints for DDR routing. I've created a simple test project to try and get my method worked out. There are just 2 chips and I have connected 3 nets between them. In Capture, i open up the net properties, go to flat nets, and invoke UI for the relative propagation delay.

After setting up a match group and loading the netlist in Allegro, I am not able to achieve any effect from the RPD constraints. Min/Max etch length seem to be fine, but no matter what I do for RPD. the Actual/Margin boxes in constraint manager remain yellow. Here is a little cut and paste from my RPD spreadsheet.

MGrp MG1
Net N249409 All Drivers/All Receivers Global TARGET 1144.00
Net N249413 All Drivers/All Receivers Global 0.01 ns:5 % 1197.00
Net N249419 All Drivers/All Receivers Global 0.01 ns:5 % 1111.00

I have tried lots of different things, like using Pin-Pairs, L/G, different kinds of tolerances, targets. I have even found some designs from other people that supposedly work, and were at least routed, although I am not sure what product version they were made with. Probably older. However, effect is the same on my setup. Always yellow boxes, always RPD ignored.

Please help if you have any ideas/advice.
Thanks,
Jon Pry
 

Anonymous_Ricky

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Hi jonpry,

i am facing the same sort of problem though other boards are workin fine my board is showing yellow boxes.
were you able to get any answer for this?
 

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