Trouble inserting level shifters with upf and design compiler

[beeflobill]

I'm working with Design Compiler and UPF to insert level shifter and isolation cells into a design. I have two power domains.

I'm having problems inserting level shifter cells.

The issue is when there is a driver with some of it's fanout in one domain and the rest of it's fanout in the other domain. I'd expect Design Compiler to split the net in two, so that each net has fanout going to just a single domain. Then the tool could add a level shifter to the applicable nets. However, Design Compiler just refuses to insert level shifters. It will not split the nets.

I do have some level shifters inserted into the design. So, I think the level shifter libraries are okay. And, I've tried many many different variations on how to write set_level_shifter statements. I'm thinking that probably isn't the issue, but I could have definityly missed something in the UPF. I've also tried removing the dont_touch attribute on everything I can see.

I have a few questions. One, is this a typical problem that people face? If so, what are the typical solutions? Two, I couldn't find any documentation that seems to apply to this issue on solvnet. Can you please point me to some documentation for this? Three, is this most likely to be an issue with how UPF is written, the level shfiter libraries, Design Compiler, or the design itself? Four, is splitting the nets like I described what the tools usually do to insert level shifters, or am I totally crazy to expect that because something else makes more sense.

Of course, question five, what the bleep is going on?

Thanks.

 

[ThisIsNotSam]

This is not a typical problem, as it is usually handled at physical synthesis level, not logic synthesis.

 

[beeflobill]

This is not a typical problem, as it is usually handled at physical synthesis level, not logic synthesis.

The tool support person gave a name to my pain, "heterogeneous fanout". They said it's a "real pain". He pointed me to some documentation on it, but it wasn't much.

I've been coping. I've found that the only way to really handle this is to go back to the RTL and manually split the ports, so each port has a dedicated fanout to a particular domain. That really helps, and it seems to be the most clean and only solution.

For a time, I was thinking that the APAR tool would be able split ports automatically, but it seems to have all the same types of issues as the compiler. It may build ports for some things, but it doesn't seem to for this. Maybe if I dug deeper for another month............

Now, I'm to the point where the only place I have this issue is with the scan enable signal. That thing is going everywhere and is a total pain, and since it's automatic, I haven't figured out how to get the tool to fix it.

But, we'll figure something out.

Thanks.

 

[ThisIsNotSam]

you can do some ECO clone operation in physical synthesis that could help you with this port splitting issue.