Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Triple well tie-down rule in IBM 65nm cmos10lpe process

Status
Not open for further replies.

chickenvlsi

Newbie level 6
Joined
Jun 4, 2009
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,397
Hi everyone,
We are using IBM 65nm cmos10lpe process.
Our design used a triple-well RF nfet (nfettw_rf). However, when we checked DRC with Calibre, the tool generated the following result:
"Triple well tie-down rule: [(T3 not over NW) touching gate] must touch RX, which is electrically connected to (RX over NW) through M1"

Could you please explain more about this rule and let me know how to fix the violation of this rule?

Thank you very much
 

oermens

Advanced Member level 2
Joined
Nov 19, 2005
Messages
525
Helped
107
Reputation
220
Reaction score
44
Trophy points
1,308
Location
canada
Activity points
3,988
You can try asking on MOSIS User Group if you got the PDK throught them:

**broken link removed**
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top