tri state output for 8bit alu

[ashwini jayaraman]

I am getting the following error continuously

Primitive output connection must be a scalar net.

please check the code below.what should I change in it.I should do only in dataflow modeling.
module alu_modify_tri(Y,A,B,E);
output [7:0] Y;
wire [7:0] F1,F2,F3,F4,F5,F6,F7,F8;
input [7:0] A,B;
input E;
tri [7:0] Y;
assign F1=8'h0;
assign F2=A&B;
assign F3=A|B;
assign F4=A^B;
assign F5=A+B;
assign F6=A-B;
assign F7= ~A;
assign F8=8'hFF;
bufif0 #10(Y,F1,E);
bufif0 #20(Y,F2,E);
bufif0 #30(Y,F3,E);
bufif0 #40(Y,F4,E);
bufif1 #50(Y,F5,E);
bufif1 #60(Y,F6,E);
bufif1 #70(Y,F7,E);
bufif1 #80(Y,F8,E);
endmodule

 

[rberek]

You have assigned an 8-bit bus (Y) to the 1-bit output of each of the bufif primitives

r.b.

 

[ashwini jayaraman]

How do I modify this code so that it has a three-state output controlled by an enable input?Can you tell me ??

 

[mrflibble]

I was busy typing it, then naaaaaaah, there is bound to be an example for this. And sure enough:

https://www.sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_body.html#8.0 Module Instances

See the "Array of Instances Example".