Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Tri State Logic- Is it correct

Status
Not open for further replies.

ship_baba

Member level 4
Joined
Aug 9, 2007
Messages
70
Helped
6
Reputation
12
Reaction score
5
Trophy points
1,288
Activity points
1,592
hi,
is this logic correct

regards,

baba
 

For what application you want to use this. For input-1 the two combinations of tri-state buffers (above n below one) stores 1 and for input-0, they store 0, i suppose.... :|
 

I suppose it would be correct if you goal is to latch all three signals high forever, but I can't think of a useful application for such behavior.
 

Wouldn't this design break something?

For example because a,a2,a1 are all bi-dir pins what if:
a = output(High) and a2 = output(High)
At the node at the topmost tri-state buffer you would have a signal going into an output i.e. =>Boom<=. Same thing can be said about a1. I do not remember what this is called, but i do know such things break pins right?
 

Wow, a classic solution looking for a problem ;-)

Lefty
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top