transmission gate switch & SFDR of track &HOLD

[wael_wael]

hi every body,
i am going to design switch capacitor track and hold, i have finished design the OTA and clock genrator. i want design the switches ( transmission gate one) could some one help my by show me the digram of design and how to simulate it. it will be so helpful to me.
thank u so much

 

[maturity]

Re: transmission gate switch ?

why do not use the boosted switch?

 

[naalald]

Re: transmission gate switch ?

Hi,
You'd better use bootstrap switches for the input switches to improve your THD. But for other switches you can use transmission gate.
For bootstrap switches this paper by Dessouky is helpful:

For transmission gate switches this paper can help you:
Low power delta-sigma Modulator for ADSL applications in a low-Voltage CMOS technology
by: Safi-Harb, M.; Roberts, G.W
This paper is here:

Hope it helps you!

 

[wael_wael]

Re: transmission gate switch ?

thank u so much guys, i have desined the transmission gate switch, but i will go to design bootstrap one i hope not taking long time, i am really looking to high SFDR.
regards

 

[wael_wael]

Re: transmission gate switch ?

dear friends, i have used transmission gate switches the problem in fact is SFDR, i cant read the result, could u help me to know how mush is it, Fin is 10 MHz, FS=50MHz
regds

 

[wael_wael]

Re: transmission gate switch ?

BY THE WAY I HAVE TO THANK" naalald" , IN FACT THE PAPERS WAS VERY USEFUL
, AND I HAVE MANY QUESTIONS ABOUT THE BOOTSTRAPPING SWITCH , EXAMPLE IN THE PAPER OF VERY LOW VOLTAGE DIGITAL AUDIO, IN FIGURE 7 HOW TO DESIGN &SIMULATE THE CIRCUIT
REGARDS

 

[mouzid]

Hi wael_wael,
Could you explain the advantage of this switch in term of speed and power consumption ?

 

[tekno1]

S.A. Wael_Wael,

If your fin 10MHz and fs=50MHz just FFT about a couple of hundred MHZ. The location that you are interested is very lower end of your plot.

 

[wael_wael]

Hi wael_wael,
Could you explain the advantage of this switch in term of speed and power consumption ?

in fact the circuit was used for very low voltage 1 v, and the Fs=5 MHz

Added after 2 minutes:

S.A. Wael_Wael,

If your fin 10MHz and fs=50MHz just FFT about a couple of hundred MHZ. The location that you are interested is very lower end of your plot.

u r right, but i am using the simulator to get FFT, so i will try to adjust it, any way i domt think the SFDR in the figure enough for 10 bit resolution, is it right?
bcs 10 bit need 60.2 db as DR
regards

Added after 8 minutes:

by the way i found very useful paper explain the switch in the figure up,
"Input switch configuration suitable for railto-rail operation of switched opamp circuits"