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Transmission Gate Simulation in Cadence Virtuoso

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knark

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i am encountering a strange problem while simulating my transmition gate which i will be using for flip flop, which will eventually be used for designing PFD of PLL.
the output gives some periodic distortion which even appears if there is no input !!
the schematic, symbol and output pics are attached
any sort of help will be appreciated
regards
 

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