Transmission gate question ?

[master_picengineer]

Hi all,

I simulated the transmission gate (Shematic bellow). Output has the same waveform that the input of the transmission gate. However I dont understand why the amplitude of this output is 0.7 V ? In fact it is expected to be 1 V.

Please help.
thanks.

 

[hr_rezaee]

Hi
sketch transistor level schematic and input and output signals.
regards

 

[Fom]

I think that's because body of transmission gate transistors are connected to sources instead of VDD and GND.
It is the most common error for transmission gate simulation.

 

[master_picengineer]

Thanks Fom,
I know that PMOS bulk is connetced to Vdd and NMOS Bulk to the gnd. But there is a problem.

 

[gaom9]

I think it is right.
In the transmission，when the transistors turn on, the difference of the voltages of the source and the drain must be a Vth at least, so I think it is right. And the transmission gate can not make the output voltage the same as the input voltage.

 

[master_picengineer]

Hi all,
The problem is in the amplitude. You see as depicted in the schematic the output voltage is between 0.9 V and 1.14 V insteed of having 0 and 1 Volt. How do you explain that gaom9.
Thanks for your replies.

 

[Teddy]

since you did not show the schematic i am guessing - I would say that you do not have power supply and GND defined by voltage source.

 

[hr_rezaee]

Hi
Where is your load? !!!
if you don't have load, the transistors are not biased.
try with load.
regards

 

[Fom]

As I see input of transmission gate is connected to 1V. So output also should be 1V. But it will be 1V when PMOS transistor of transmission gate is ON (NMOS is OFF). When PMOS is OFF and NMOS is ON the output will be floating. And it bounces up because of capacitance coupling.

 

[gaom9]

I am sorry I only pay attention to your description on top. Did you add the power supply to the inverter and to the CMOS transistor? Or did you connect the power to the ground, so the output will not be pulled to ZERO? You can post the SCH or the netlist here. I think it will help, what we need is not the picture your post before but the SCH or the netlist.
Best regards!

 

[master_picengineer]

Hi all,

Thanks for your replies.

As I see input of transmission gate is connected to 1V. So output also should be 1V. But it will be 1V when PMOS transistor of transmission gate is ON (NMOS is OFF). When PMOS is OFF and NMOS is ON the output will be floating. And it bounces up because of capacitance coupling.

That's rigth. That's what I liked to hear. Thanks for the details.