[SOLVED] Transmission Gate Delay

[Engineer4ever]

Hi,

I am designing a PFD/CP/LF in a PLL loop. I need to connect the PFD output to the CP input, but my CP has two inputs; UP and UP-bar and the same for DOWN signal. The delay between UP and UP-bar is one inverter delay, so the UP-bar signal leads the UP signal by a delay of one inverter but I need both signals to arrive at the CP input at the same time so I need to pass the UP-bar by a transmission gate with the same delay of the inverter. My question is, how to determine the transmission gate delay? Is there an equation for it?

Note: I am working on 65nm technology in case that matters.

Thanks in advance,

 

[AdvaRes]

Hi,
See Page 11:
**broken link removed**

 

[Sang-ki Lee]

Hi.
I know how to solve delay problem because of inverter delay.
Using 'latch-buffer', I solved the problem.
It can make the UP-bar & UP signal without delay. (same Down signal)
good for you!

regards,

 

[Engineer4ever]

Alright, thanks