translate 500Mhz sineusoidal waveform to 1.262MHzTTL ？how？

[zhup]

I am looking for a solution to translate 500Mhz sineusoidal waveform（10dBm）, to
1.262MHz TTL level. The supply is -/+5 Volt.
I know using AD9500 can do this work：translate 500Mhz sineusoidal waveform（10dBm）, to 250MHz ECL level,but how to do the next？. Please help,

 

[keith1200rs]

I'm puzzled. What is the required relationship between the 500MHz signal and the 1.262MHz one? They aren't harmonically related. You could mix 500MHz with 501.262MHz to get 1.262MHz. Is that what you want?

Keith.

 

[davenn]

I'm puzzled. What is the required relationship between the 500MHz signal and the 1.262MHz one? They aren't harmonically related. You could mix 500MHz with 501.262MHz to get 1.262MHz. Is that what you want?
Keith.

My thoughts exactly, Keith, or at least downmix to some convienent freq and then use a prescaler IC to get the final division and a TTL output

cheers
Dave

 

[bepobalote]

Can't you use a DDS to get the required frequency?

 

[tony_lth]

1. mix 500MHz with 492.8M to get IF1=7.2M
2. Use MC12009 to divide-by-6 IF1 to get IF2 TTL output of 1.2M
you can also select divide-by-10 IC, so IF1 should be 12M, that maybe easier to filter IF1

 

[BigBoss]

500e6/1.262e6=396.196513
You need a fractional divider to get this frequency..
Integer part will 396 and fractional part will be 0.196513.
But unfortunately, it's hard to find a "fractional divider" standalone but you can create this frequency with a fractional PLL..
So, divided frequency will be exactly the frequency which you want eventough th PLL will never be locked :wink:

 

[zhup]

thank you ,keith1200rs!the relationship between them is that the division is 396,and 500e6/396=1.262e6,roughly

---------- Post added at 11:40 PM ---------- Previous post was at 11:35 PM ----------

thank you davenn !but the input freq is only 500MHz.

My thoughts exactly, Keith, or at least downmix to some convienent freq and then use a prescaler IC to get the final division and a TTL output

cheers
Dave

---------- Post added at 11:45 PM ---------- Previous post was at 11:40 PM ----------

thanks bepobalote! I am embarrassed,but I know litter about DDS ! Do you think this is an effective solution？

Can't you use a DDS to get the required frequency?

 

[bepobalote]

to my knowledge it can be one of the best solutions: one DDS (maybe from Analog Devices) and one small chip to program it, some components for the oputput filter (not too demanding because the output frequency is very low) followed by a squarer...
Price: not more than 20-30 dollars (for one complete unit), and the provision to set your output frequency even in microHz steps!!!

Unfortunately now I'm not at home, so I'm unable to give (until tomorrow) you more documentation regarding DDS.
I suggest you to check Direct Digital Synthesis ( DDS) & Modulators | RF / IF ICs | Analog Devices for the following products:
AD9958, AD9911, AD9959, AD9858, AD9910, AD9912, especially the last two.
In the datasheets you will find some sample schematics which can be useful to recognize the simple circuit needed.

 

[millwood]

dividing by 396 is easy. dividing by 396 at 500Mhz is very difficult.

your likely chance is with fpga devices or asic.

 

[FvM]

The original poster hasn't answered the question, if a rational :396
divider would be acceptable. In this case, it's almost easy.

 

[keith1200rs]

If it is divide by 396 I think I would use a synthesizer. I could be done with dividers but I think a synth is probably easier. I don't know about DDS though, so that could be a better solution.

Keith

 

[zhup]

thanks FvM,I am very sorry I could made myself clear,500Mhz sineusoidal waveform ,396 divider,and how to do it ? Do you have effective solution? !

---------- Post added at 08:36 AM ---------- Previous post was at 08:32 AM ----------

thanks keith1200rs again,is there a 396 divider for 500Mhz sineusoidal waveform ,and output TTL level?

---------- Post added at 08:40 AM ---------- Previous post was at 08:36 AM ----------

thanks millwood, I know there is two PLL in fpga, but can it do that dividing by 396 at 500Mhz ?

 

[tony_lth]

That's very easy. Use MC12013 divide by 11, then use MC12009 divide by 6, then use MC12009 divide by 6. So that's divide by 396.

 

[zhup]

thanks tony_lth,I will ckeck the MC12013\MC12009 datasheets!

---------- Post added at 08:49 AM ---------- Previous post was at 08:46 AM ----------

thank you bepobalote ,Iwill learn this documentation regarding DDS,and try to do !

 

[bepobalote]

I suggest you the following readings:
https://www.ieee.li/pdf/essay/dds.pdf
https://www.analog.com/library/analogDialogue/archives/38-08/dds.pdf
**broken link removed**
**broken link removed**

Just as an example, please take a look at the following schematics:
DDS-60 Kit from the AmQRP
even if you will have to use a different DDS chip (this one is rated for 180 MHz max freq.), the schematics will remain almost the same!
As you can see, using a DDS will require very few components and if your DDS has an internal comparator, you will be able to square its output without any additional chip.

P.S. I have to admit that you will take some more time to understand its internal working and programming but to me it is worth the wait

 

[zhup]

Thanks bepobalote for your support and help all the time,I will try myself to do the valueable work,maybe in this process I also ask you some childish question!Thank you again!

 

[bepobalote]

Sorry, but I discovered that in the references I gave you, I pasted a wrong link: here it is the corrected one (to me it is the most interesting among them):
http://www.ieee.li/pdf/essay/dds.pdf
I have also provided to correct my previous post

[added some minutes later]
Please take a look at the following DDS project: it works with a 500MHz clock (like in your requests)!!!
http://www.i0cg.com/ad9951.htm
**broken link removed**
AD9951 page
http://www.sdradio.eu/doc/1_GHz_clock.pdf
BTW, you can contact Giuliano: maybe he has some spare PCB for his DDS (in case you want to test it) :wink:

P.S. I suggest you to search for the words "dds i0cg" to get more info about this project.

 

[volker_muehlhaus]

I am surprised to see the DDS mentioned here. A DDS is nice to create a variable frequency output, if you can accept a certain level of spurious signals. To me, it makes absolutely no sense to create a fixed frequency in the MHz range using a DDS.

---------- Post added at 06:52 AM ---------- Previous post was at 06:44 AM ----------

If it is divide by 396 I think I would use a synthesizer. I could be done with dividers but I think a synth is probably easier.

Why is a synthesizer easier? A synthesizer requires the divider plus additional components to form the phase locked loop.

 

[FvM]

I am surprised to see the DDS mentioned here.

You are absolutely right. The DDS idea came into play, because the original question didn't clarify, if the intended output frequency involves a rational division factor. If it's the case, also the DDS output can be spectral pure, not containing spurious components, but not necessarily. With a usual binary accumulator, it wouldn't. It's a waste of resources anyway.