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transistors in linear region

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Junior Member level 2
Apr 22, 2009
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i have a circuit with as many as 8 transistors in the linear region, how to analyse these transistors without small signal model

how to decide W/L ratios for these transistors ?

any suggestions plz, thank u

simplybharath said:
without small signal model

how to decide W/L ratios for these transistors ?

I dont think there is any general method for that. If you dont want to use small signal because of higher signal amplitudes then you will have to take into account the variation in dc operating point, you will perhaps have to repeat the small signal analysis at different dc points. Still I think it would be better if you could show the schematic or tell what circuit it is?

For W/L, you will may calculate them from small sig. assuming the Mosfet as resistance but I am not sure of this for large signal.

correct me if I am wrong.

- zopeon

my ckt is already posted in the forum by the name analog multiplier topology....

here in this ckt all the NMOS's are linear region. the paper in the ckt says that increasing kp/kn ratios reduce the linearity and increases the noise

but the author of the ckt uses a w/l ratio of .8u/.35u but doesnt explain y he chose that only.

it will be really helpful if u cud help me in analysing the ckt

Added after 1 minutes:

sorry in the above thread i made a mistake in saying actually increase in kp/kn ratios reduce the noise

Kp/Kn is different than W/L, and flicker noise will depend more on L than on W ( for same values). So if you are increasing the L, then it will reduce noise as stated. Nmos has more noise than pmos but apart from that I am not aware of effect of Kp/Kn on noise but if thepaper talks about increasing Kp keeping Kn constant then its becoz of higher W*L for Pmos. ( But will perhaps increase if you compare it with a reduced Kn value and constant Kp value)

- zopeon

I'm not sure about the working of this circuit. But I can tell that transistors M1, M2 M3 M4 have more chance to be in linear region since its gate is connected to the highest potential, VDD.
If Vp1,2,3,4 nodes are swinging the then M1-4 will go to linear region.


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