Transistor Stability at Low Frequencies

[EEPC]

Hi all,

For LNAs what are good ways to stabilize the transistor at low frequencies? I'm working on an LNA and observe that its stability factor (K) is essentially 0 around f = 0 Hz (I'm using ADS to simulate K) and then quickly jumps up to a high value before coming down again. I'm wondering if what I'm seeing is just something weird happening in the simulation or if it means that the transistor is actually unstable at DC. I attached a picture of the K plot:



Note: K remains greater than 1 for all higher frequencies, so it's just in the range between 0 to ~90 MHz where it is below 1.

Right now my stabilizing network consists of some resistive loading at the drain (output) and some small source inductance. I find that if I add some loading at the gate (input) as well then K goes above 1 at lower frequencies, but this severely degrades my NF.

Any suggestions are welcome! Thanks.

 

[biff44]

Pretty much any transistor that has high gain (like 15 dB) at microwave frequency is going to have a HUGE amount of gain at low RF frequencies (like 30 to 50 dB). It is that excess gain that causes the instability.

You can use filtering mechanisms in the base and collector bias structures to terminate the base and collector in the right impedance at these lower frequencies without screwing up the microwave operation too much. Also, since your problem is at low frequencies, sometimes it is easy to apply some negative feedback at the lower frequencies to help to kill that excess gain.