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Transistor Sizing Tools

neycalazans

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I am interested in using and developing transistor sizing tools for digital design, either for creating specific standard cell libraries and/or to produce a sized digital transistor network for CMOS technologies.

Does anyone knows about commercial or open source tools to perform transistor sizing for CMOS digital networks?

We have developed some in-house approaches for automatically sizing transistors in my research group (a combination of sizing heuristics and also software to perform sizing according to some performance/power/size criteria), and we would like to compare our heuristic/tools results with other approaches.

I can find many publications in the literature about transistor sizing in the sense I explained above, but no link to specific tools available.

We have access to Cadence, Synopsys and Mentor University programs, but I could not find a sizing tool or even some embedded sizing functionality into some tool from these vendors. We are used to design ASICs using standard cell libraries where differently sized gates already exist and are employed by synthesis tools like Cadence genus or Synopsys DC. But we do need to create our own gates or transistor networks in general, and we know the effect of transistor sizing is significant on the final circuit.

Ney
 

dick_freebird

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I recall from way back when, that library compiler
point-tools within Cadence would support some
W optimization to goals (but not that automated,
building the testbenches was still on you, as was
the articulation of goals and parameter ranges
etc.).

What today's toolbox holds, I do not know / care.

I prefer to focus on critical paths and go at it
old school (just Spectre / SPICE and parametric
loops, with as much realism as can be had).
 

ThisIsNotSam

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Oi Ney, vou responder em ingles abaixo :)

the sizing problem is not really a problem a lot of people care about. there are maybe 3-4 companies that still develop standard cell libraries (ARM, TSMC, Synopsys, ...). everyone else just takes pre-sized standard cells and lets STA pick the driving strength using whatever internal optimization engine they have.

Still, that being said, the old FO4 metric is still reasonable for everything above 22nm. Below that, in the FinFET era, transistors have immense driving currents, so the ratios are sometimes hard to interpret. The sizing is also done in increments of fins, which makes it a discrete optimization problem. It's not rocket science.
 

neycalazans

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I in part agree with both answers above (by dick_freebird and ThisIsNotSam), and although not saying that explicitly, they clarified me (and confirmed my suspicions) about why there is no generic sizing tool out there, commercial or not.

Yet, the digital design spectrum is not composed by standard cells alone, right? There are other approaches that might be feasible, like regular fabrics, creating dedicated cells for specific projects and so on. I still think that a generic tool, if sufficiently parameterizable by user-defined cost functions, might save a lot of analysis and trial-and-error sizing.

In particular, we work with cell libraries for asynchronous QDI design, and there is no such library available supporting this kind of design style, except those that we did developed, such as https://github.com/marlls1989/ascend-freepdk45, and others we cannot make open-source due to NDA signing. QDI design requires a set of cells including some large transistor networks (reaching several dozen transistors).

We managed to optimize the sizing of cells in commercial libraries using an in-house tool (according to some user-defined desirable performance characteristics), which shows me that for some specific need a fast executing, easily parametrizable sizing tool might be quite useful.
 

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