Transistor sizing-cascode gain stage-noise performance

[ricopt]

anyone know how my transistor sizing W/L affect my noise performance ?

From what i simulated out

My result is when i using W=45, L=0.18, my noise is 3.14pA
while W=44, L=0.18, my noise is higher, which is 3.15pA

From what i research, it should be lower rite ?

if we decrease transistor sizing W/L ratio, transimpedance gain will increase, and noise will be reduced .

Can someone clarify for me ?

Thanks
any reply are greatly appreciated

 

[mvj]

Noise is inversly related to the Area of the transistors. So when u reduced the width from 45 to 44 the area WL reduced and hence the noise increased.

 

[ricopt]

Is there any reference that i can refer to regarding sizing and noise ?

Then is W/L increase, bandwidth will decrease is it correct ?

How its affect transimepdance gain ?

 

[mvj]

- You can refer to Razavi, chapter on "noise". Flicker noise to be more specific. Flicker Noise is modelled as a voltage sourse whose magnitude depends upon transistor area "WL". You can then look into thermal noise as well.
- No, the bandwith increases. As you increase W/L, current increases( which can be considered as a decrease in the effective output impedance) and since the output impedance decreases the gain decreases. Product of gain and bandwidth is a constant, since the gain decreased the bandwidth increased.
Another way of looking at it is - as w/l increases, current increases so now there is more current to charge and discharge the output capacitance. This mean that it would now take less time to charge and discharge the capacitnaces so it is much faster and hence it can be used at relatively higher frequencies i.e. an increase in the bandwidth.

- gain decreases as i mentioned above.

 

[ricopt]

thanks bro