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Transistor size and capacitance

mirror_pole

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Hello guys, i have a question concerning node capatitances and transistor size.
In the book Design of analog integrated circuits and systems by Laker and sansen i saw an equation which expresses the relationship between node capatitances in a circuit and transistor size: Cn=Cn,0+k*W/L. Cn,0 and k are CMOS process related. I would like to know where this formula comes from. Cn is the total capatitance related to a node.

Im a bit confused as well because in razavis book design of analog integrated circuits i saw different expressions for the capacitances, also dependent on the region the transistor is operating. For example in saturation CGS=2/3*WL*cox+WCov.
 

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