transistor model in SPICE simulation

[oAwad]

Hello all,

When I use high performance transistor model with a design SPICE netlist (generated from std cell design flow), I get the correct results in SPICE simulation. However, when I try to use low threshold transistor model, I get wrong results.

I just replace the "NMOS_HP" file with "NMOS_VTL" (with changing the transistor model for all the cells in the design SPICE netlist), so what might be the problem ?

I'm using HSIM for SPICE simulation.

 

[ThisIsNotSam]

Are you including the right model file? What error are you seeing?

 

[oratie]

If you have sequential cells in you netlist (flip-flops), you may get hold violations. Because VTL transistors are faster.

 

[dick_freebird]

What is "wrong" about the results, and how do you
know the results are "wrong" rather than "undesirable"?

 

[oAwad]

If you have sequential cells in you netlist (flip-flops), you may get hold violations. Because VTL transistors are faster.

How is VTL transistors are faster ? I thought that high performance transistors are faster on the cost of leakage, while VTL have lower leakage (low power) on the cost of speed.

 

[ThisIsNotSam]

How is VTL transistors are faster ? I thought that high performance transistors are faster on the cost of leakage, while VTL have lower leakage (low power) on the cost of speed.

You got this wrong. Low VT transistors are faster, and leak more. High VT transistors are slower and leak less.

 

[oratie]

VTL = voltage threshold low (high speed, high leak)
VTH = voltage threshold high (low speed, low leak)