When I use high performance transistor model with a design SPICE netlist (generated from std cell design flow), I get the correct results in SPICE simulation. However, when I try to use low threshold transistor model, I get wrong results.
I just replace the "NMOS_HP" file with "NMOS_VTL" (with changing the transistor model for all the cells in the design SPICE netlist), so what might be the problem ?
How is VTL transistors are faster ? I thought that high performance transistors are faster on the cost of leakage, while VTL have lower leakage (low power) on the cost of speed.
How is VTL transistors are faster ? I thought that high performance transistors are faster on the cost of leakage, while VTL have lower leakage (low power) on the cost of speed.