Feb 23, 2012 #1 V veena15 Newbie level 1 Joined Feb 23, 2012 Messages 1 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,285 HI The primitive tranif0 and tranif1 are not support by Xilinx for synthesable design ,but my design needed to implement the function of primitive "tranif0 or tranif1 " for example if C is 1 , A <=>B(bidirectional transfer ) , else C is 0 thank you !
HI The primitive tranif0 and tranif1 are not support by Xilinx for synthesable design ,but my design needed to implement the function of primitive "tranif0 or tranif1 " for example if C is 1 , A <=>B(bidirectional transfer ) , else C is 0 thank you !