Transient response of the vco control voltage of a PLL

[analog_ambi]

Hi,
1. I have attached transient response of the control voltage of my PLL in Cadence. This is NOT behavioral reponse.

2. From t=0 to 100us it is the startup time. No frequency step provided

3. At t=170us a frequency step of 40MHz (max size for the pll) is provided and resulting transient response is shown.

The startup response saturates to VDD and then settles. Is this a problem?

Is the freq step response OK for phase margin of 60 deg.

 

[crutschow]

Can't tell the phase margin without the Bode Plot, but from the observed oscillations and overshoot I would think your phase margin requirement is not being met.

Post the schematic.

 

[LvW]

analog_ambi,

I think the graphic tells nothing about the phase margin.
Phase margin is a parameter that applies to the linearized PLL in LOCKED condition only.
But your graph clearly shows a kind of lock-in process, which obviously does NOT depend on the phase margin.

 

[crutschow]

analog_ambi,

I think the graphic tells nothing about the phase margin.
Phase margin is a parameter that applies to the linearized PLL in LOCKED condition only.
But your graph clearly shows a kind of lock-in process, which obviously does NOT depend on the phase margin.

Don't understand your reasoning. If the PLL is going from one locked frequency to another while remaining in the linear state (step function change), then overshoot and ringing of the loop typically indicate a poor phase margin.

 

[LvW]

Don't understand your reasoning. If the PLL is going from one locked frequency to another while remaining in the linear state (step function change), then overshoot and ringing of the loop typically indicate a poor phase margin.

...remaining in the linear state?
How do you know?
I think the shown waveform does not support the assumption of a linear state.

 

[crutschow]

...remaining in the linear state?
How do you know?
I think the shown waveform does not support the assumption of a linear state.

I can't know for sure of course, but the waveform looks like a linear step function with overshoot and ringing. I don't seen signs of signal saturation or other non-linear characteristics. What do you see that makes you think it is non-linear?

 

[FvM]

the waveform looks like a linear step function with overshoot and ringing.

I don't think so. Have you ever seen ringing with ascending and descending amplitude? I would interpret the average value as the step response with an superimposed charge pump ripple. The ripple is apparently proportional to the phase detector error.

The step response shows a fair overshoot, which could be understood as an acceptable phase margin of the continuous time equivalent transfer function. But I'm partly guessing.

 

[saro_k_82]

As long as the loop does not lose lock during the step, linear assumption would hold quite well. The response shows no sign of losing lock., only overshoot, but I guess it could be designed for better stability