Transfer function of PFD

[ack88]

Hello,
Thanks in advance for reading.
I am trying to find the transfer function of a PFD block in a schematic of PLL in Cadence Virtuoso .
How can i find the transfer function of PFD block?
How can i sweep the input phase difference to get the transfer function?
- Thanks

 

[saro_k_82]

Why would you need that? Assuming that to be a scalar (KPFD) is good enough for the cases I have seen. You can be concerned about the non-linearity of PFD rather (which can fold back noise in to the spectrum around carrier) which will not be provided by the transfer function.

 

[varunkant2k]

PFD block transfer function includes from PFD to Charge pump. PFD input variation is delta phase-shift (delta-phi). Charge pump out is Ipump for 2*pi radians phase shift. transfer function will be: Ipump/2*pi.

 

[ack88]

Saro_k_82 : thanks for the reply , i used the linear approach to calculate all the gains for the given PLL but i am not getting the required output .So i was trying to get exact relation between the the 2 inputs of the phase detector .
Do you have any approach so i can get the exact nonlinear nature of the PFD ?

 

[ack88]

These are the plots i obtained from VCO and PFD.
how should i adjust the gain of PFD so that i get the required frequency at the output of the VCO.

 

[varunkant2k]

I think your VCO gain is non linear. VCO need to adjusted. From PFD to charge pump as long as you are following dead time (of charge pump switches from PFD UP/DOWN signal) correctly should not be the problem. Yes current should follow the low pass filter requirement.

 

[saro_k_82]

A non-linear gain for VCO is acceptable as long as it is monotonic (If you look for linear VCO much better than you currently have, you may never end your design phase). It is the non-linearity of PFD that can cause noise components to fold in to your spectrum.
Your PFD transfer curve is not monotonic, which can cause serious problems that your PLL may never lock if there is large enough phase difference to start with.
In the linear region it looks very linear (if you had sufficient points in between), so that should not be in your list of your problems. If you are not designing a fractional-N PLL, the PFD linearity requirement would be more relaxed (but slope changes are not allowed)

Just fix the phase of one input and sweep the phase of the other input and look at the voltage at the CP node to plot the transfer curve

 

[ack88]

Thank you guys for the reply.
The above PFD plot was plotted the same way , i have varied the fb input with +Pi keeping the reference input constant.
The problem i am having is that the system gets in phase but the VCO output frequency is not the frequency i expect.
Now,
I have given Clkin as 6MHz,and i have used multiplier of 4 in the loop . So according to the formula i should get 24Mhz as output , but I am getting 45Mz as the output and avg(Vc) is about 0.9 V

 

[ack88]

Is there a specific relation between change of frequency in the two inputs and the phase error?

 

[saro_k_82]

I think your problems lies elsewhere. PFD is the last block that can change your multiplication factor. Check the other blocks - fb divider, CP, LPF-leakage and VCO