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Track and Hold circuit realization

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Newbie level 3
Sep 23, 2007
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Hi all,

For my project I have to design a Track and Hold amplifier in cmos 0.18-um process. I am simulating this in ADS2005A.

Specifications are:

Vsupply = 1.8V
Closed-loop gain = between 0dB and 12dB (1 to 4). Dont have to be adjustable.
Vout,swing = 0.6V (peak)
Cload = 5pF
SNR ≥ 70dB
THD ≥ 70dB @ 100MHz
Sampling = 200MS/sec

I know how to design a cmos amplifier, but I have never designed a Track and Hold amplifier. I don't know how to start realization of the circuit for Track and Hold. I think I need a Track and Hold circuit and a amplfier stage (two-stage probably) for this project. Maybe also output stage, but I am not sure about that yet.
I found out that I have to use a clock signal for the Track and Hold circuit. According to specs, sampling = 200MS/sec. What does mean for the clock input of the Track and Hold circuit. Is the clock frequency also 200MHz? What is the amplitude of the clock, also 1.8V (peak-peak)?

I have found a Track and Hold circuit (see attachment). Cs is the sampling capacitor and CL is the load capacitor. I don't understand what the opamp in this circuit is doing. Is that the op-amp I have to design for open-loop gain?

Help me out guys, I am really stuck:cry:. Thanks a lot!!!



If you need Closed-loop gain = between 0dB and 12dB (1 to 4). I think the ciurcuit in attachmet does not fit for you. As you need program gain amplifier. It is only 0dB track and hold.
SNR ≥ 70dB THD ≥ 70dB @ 100MHz mean you need about 12bit precision. So the gain error and bandwidth affect must less than -70dB. That mean your loop gain must larger than 70dB. Bandwidth limit error mut less than -70dB(about 1/4096). ΔVgain=1/βA ΔV(bandwidth)=exp(-t/ζ) where ζ=1/RC=1/ω3dB
clock frequency is also 200MHz. You need design a no-overlap clock circuit.
a amplfier stage (two-stage probably) for this project.
If you use two-stage op, the close loop stability maybe is a challenge.
So i think use gainboosting op or open loop sample when use two-stage op.

Detail you should reference some paper.
The 12bit 200M the switch and op design are large challenge. you should reference some paper. Such as paper about pipeline ADC.
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Hello jerryzhao,

Thanks for your reply.

Actually, the closed-loop gain doesnt have to be programmable; closed-loop gain of for example 0dB is ok.

If the track and hold circuit has a closed-loop gain of 0dB, then it is enough I think; maybe it is not exactly 0dB.
However, is the realization of the amplifier part of the Track and Hold circuit just a diff. pair with differential input and differential output?

If I, for exmple, build a cmos opamp with a large open-loop gain, will this be the opamp symbol in the Track and Hold circuit?

One more thing: What do you mean by no-overlap clock circuit?



The op need differential.The input can diff or single with Vref the output is differential.
you should calculate loop gain then get the gain of op, this op is the opamp symbol in the Track and Hold circuit.
The no-overlap clock. It is mean the track clock and hold clock's high level are not overlap, such as Φ1 and Φ2. Φ1 and Φ2 can not high at the same time.
The clocks are not simple invert, they need no-overlap.
about Φ1 and Φ3. Φ1=Φ3 but Φ3 must turn off first, in order to cancel the charge injection of Switch Φ1.

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