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trace width calc

Nbj123

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Hello,

I am designing an RF PCB. I have some queries regarding PCB designing/.
how to calculate the width of the trace(Transmission line). I have used one online calculator but in that calculated trace width is bigger than PAD of IC. so in that case what I have to do.

Please guide as soon as possible.

Thanks
 

vfone

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Use this free transmission line software from Cadence:

If your printed transmission line is thicker (lower impedance) than the termination you want to connect (higher impedance) you can use a step width tapering, as in shown in the picture.
 

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volker@muehlhaus

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but in that calculated trace width is bigger than PAD of IC. so in that case what I have to do.

Controlled line impedance matters if the line has relevant length, compared to the wavelength. Only then, transmission line effects become relevant.
If the line (or part of it) is short compared to the wavelength, then it is not critical to have the exact width.

Example: 2.4 GHz -> wavelength in air is 122mm -> wavelength in FR4 is approx. 60mm
If your line is shorter than 1/10 of that, you don't need to worry if your line is narrower than calculated. Use the calculated width if you can, but it's not critical then. You can also taper width towards the pad.
 

vfone

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Using three transmission lines on FR4, h=1mm, one 50 ohms, one 90 ohms, and one 115 ohms, each 6mm long (1/10 of 60mm), an EM simulator shows huge differences in S11 and S21.

In RF, the impedance of the transmission lines always matters, more or less...
 

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volker@muehlhaus

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Ok, thanks for the example that lambda/10 is too much. I should have written lambda/20 as I usually do, and given the full math from my transmission line analysis appnote.

The important part is "more or less", depending on l/lambda

impedance_transform.png

For practical purposes, we sometimes need narrow width at the pad, and SMD like a series C (for DC block) will also have width smaller than 50 ohm line. Transmission line effect becomes important when tan (2*pi*l/lambda) isn't small, so small length of incorrect width can be used.

I agree that the taper is the way to go for the small pad.
 

vfone

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Lamda at 2.4GHz is 12.5cm (125mm), which means that 125/20 = 6.25mm, which is even longer than in my presented examples.

I heard many times this story in the last, let's say, 25 years. Many Analog (low frequency) IC designers when they switched to RFIC design, keep saying that doesn't matter the impedance of the transmission lines, if they are very short. This story its like a disease, keep coming back and back again..
 

volker@muehlhaus

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Sweetheart, I have a PhD degree in RF engineering and do that job for 30 years ... Just tried to emphasize that length matters.

Your last post is wrong because you calculated wavelength in air, and forgot to include permittivity.
 
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vfone

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I know you have, is written in all the links you post all around, when you cry for clients for your consulting company. Should be a rule on this forum placing free advertising.

Regarding appellative you addressed to me "Sweetheart", I can replay only with a quote from Scarface:
 

FvM

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The lamda/10 rule of thumb says that a circuit can be treated as lumped below this size. It doesn't say that you can always ignore the effective inductance or capacitance created by interconnects.
--- Updated ---

A tapered microstrip line creates a series L and a respective mismatching (presumed the pin represents an exact Z0 termination). More generally, the L and C elements created by the interconnect must be considered in an exact matching circuit calculation.
 
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volker@muehlhaus

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The lamda/10 rule of thumb says that a circuit can be treated as lumped below this size. It doesn't say that you can always ignore the effective inductance or capacitance created by interconnects.

Yes, you are right and vfone pointed that out with his example. I should have written lambda/20 there. The equation above is indeed the impedance transformation for a line. If you check with lambda/20, mismatch is moderate if the line width isn't exact.

If vfone isn't happy with my posts here, and considers my contributions advertising, let's just delete my account here. There are so many EDA guys who like my appnotes, I really don't need this platform for "advertising".

PS: I can understand that the way how edaboard shows the link to my appnotes looks like advertising, but those are plain links to application notes. I would also prefer them to appear as simple links. Somehow this forum software converts my hyperlink to a decorated format. That display style (with consulting mentioned on the top level page) is not created by me, it is not created on purpose and didn't happen in the old edaboard software. If there is a way to just put a plain link, that remains as is, let me know. edaboard has no business value and no advertising value to me.
 
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ktr

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I have no idea why this thing became out of hand this fast. I really like both of your advices and listened both of your advices more than once. Can't you get along nicely? Along with a couple of more guys; you two are among the best guru's here.

Now, back to engineering topic. I found and modified an optimizer for a Transmission Line self-inductance calculator; I found out that for a Rogers4350B 10 mil substrate with 20 mil trace width and 1 mil thickness of copper; there is 0.7nH inductance per 100(2.5mm) mil of trace. Permittivity of the substrate is given as 3.66 in the datasheet of device; however effective permittivity is 2.7~2.8 by my calculations. Is this a reasonable result ?

Should I take this inductance into account even for tapering sections between trace and pad of IC?
 

JohnBG

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Hello,

I am designing an RF PCB. I have some queries regarding PCB designing/.
how to calculate the width of the trace(Transmission line). I have used one online calculator but in that calculated trace width is bigger than PAD of IC. so in that case what I have to do.

Please guide as soon as possible.

Thanks
would you please 1st of all define/show the circuit you want to build on PCB?
 

FvM

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Should I take this inductance into account even for tapering sections between trace and pad of IC?
The question can be only answered related to your application requirements. I should be noted that the package impedance parasitics are also part of the matching circuit. If the IC manufacturer specifies a port impedance, he should also define a reference layout showing how it has been measured.
 

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