total resistance? electric engg anyone?

[draz]

Hi,

I have a doubt regarding Star formation and Delta formation of resistances.

Can anyone explain whether the resistance is more in star formation or delta formation of res? also is there any good doc on this.


I heard star formation has res = r +r +r
and delta has it res = 1/r +1/r +1/r


something on that lines....plz some one help me...

i think i am majorly going wrong somewhere



Thanks
draz

 

[draz]

Re: total resistance in route? electric engg anyone?

come on guys....atleast someone reply

any electrical site or something atleast

 

[verilog_coder]

This link might help you.
**broken link removed**

b/w you should post this message in elementary electronic questions

 

[draz]

Thanks a lot mate.

Actually i am using cadence First encounter for routing. Now for doing manual routes for PLL's i was told to do routing in star formation.

So thats why i was totally confused as to why this requirement was there.

If any one else can comment it would be very much appreciated

 

[xxargs]

Thanks a lot mate.

Actually i am using cadence First encounter for routing. Now for doing manual routes for PLL's i was told to do routing in star formation.

So thats why i was totally confused as to why this requirement was there.

If any one else can comment it would be very much appreciated

Ehh... you design PLL-circurits but have no any know of RF- and transmission theory ??

Is not only resistance in route you need take accont, you have traveling wave and delays on route if you working with high frequency as around PLL and make phase noise etc. if not handled well.

good grounding very near active component, star configuration etc. is way to controll of situation so unwanted traveling wave and different delay not affected PLL etc. so much.

You can always use recommend 'recipe' from book, but is better for future layout design if you learn and understud why needs make this. ie. learn RF, transmission theory for understand why talking of impedances on traces, reflection on traces or port in components, stub and 'T' affected on signal quality, coupling and radiating between traces and how important grounding are, and this effect very connected to used higest frequency in your design.

If using 10 MHz crystal and make square wave from it, you have also 30, 50, 70, 90 MHz and higher frequency traveling around your board more or less and whole frequency range need handle correctly if you still want pure square wave in destination point...

---

If routing for RF-circurit - you learn trace width and length, board thickness to ground layer, how to drawing near other traces etc. is very importent if you make success or not, and board layout is same critical componet as rest of RF-component mounted on board. Board layout in days for high frequency is passive advanced network and matching block between aktive component using different width and lengt of trace - very often called microstrip or stripline design..

(trace called microstrip or stripline if you know exactly what you a doing, and only 'trace' or 'route' if don't know, but still have affect signal on trace ;-) )

---

- And if using smaller/more big thickness between ground layer and traces different to design rules ( board maker make misstake or different material) can ruin whole board and impossible to fixing afterwards mha. tuning...

Crystallic/ceramic filter not working well if designed for 50 Ohm trace, but board makers misstake give only 20 Ohm impedance on trace, even if trace lengt is only 10 mm...

 

[draz]

Thanks xxargs,

but somehow i couldnt grasp what you were saying...probably our english dont match.

secondly i am not working on pll design or rf

just that in the top level chip floorplaning i have some pll blocks which need to be connected with power pads

only guideline for me is that this connection whould be in star/wye formation

so i was wondering what could be the reason for this