Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Topologies for a discrete 1-bit DAC for high end audio

Status
Not open for further replies.

PowerDAC

Newbie level 3
Joined
Feb 19, 2008
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
nr Oxford UK
Activity points
1,334
1-bit dac

I have implemented the digital part of a high end audio DAC in an FPGA. It is a single bit Delta Sigma design and an FFT of the output bitstream reveals this is working well. I now have to design a top-quality 1-bit DAC to convert the digital bitstream to an analog signal. The circuit will be implemented from discrete IC's or parts, not in an IC.
I'm aiming for a dynamic range of at least 125dB.
Bit rate is 12.288Mbps (256fs).
I have reclocked the FPGA bitstream output externally from the 98.304MHz low jitter oscillator, in a reg fed with an ultra-clean VCC so the bitstream itself has low jitter.

I considered the following ideas:

1. Switched capacitor integrator. This seems to be done quite often on-chip, but will a discrete design be able to realise good enough performance? The output of the SC filter would hopefully have low enough slew to feed into a conventional CT active filter. Are there any any practical guidelines for design of such circuits? The literature I've found seems to assume you're doing it in an IC or are interested only in the math, and that all components are ideal.

2. Switchable current source into ??? Ideas? Suggestions?? I would have thought that changing a fast voltage slew into a fast current slew wouldn't be of much help, but ???

3. Precison low noise reference (eg Walt Jung's 1.25nV/rtHz circuit) switched with a small switching bridge into a passive differential-in differential-out pre-filter. Bridge switches would be driven from the bitstream converted to RZ (return zero). I would hope the RZ format would ensure each symbol's rise and fall times would be repeatable. The output from the passive filter should have slew low enough to feed into a conventional diff input active filter.

4. Something based loosely on 3 but employing resonant circuitry to created perfectly repeatable pulses of a raised cosine shape.

Does anyone have any ideas or suggestions on this circuit? Anyone have experience in the topologies used for such high end DACs who could point me in the right direction?

Thanks in advance
 

discrete audio dac

Did you check, if a more basic one bit DA doesn't already achieve sufficient linearity? Dynamic range as such shouldn't be a real problem, I think. Generally, conventional active or passive CT filters seem to be first choice. You didn't mention the intended filter characteristic, but it's not that complex, I guess.

As a more general question: If you are able to effectively keep also all nonlinear effects below the 120 dB floor, does in have any relevance for audio reproduction?
 

discrete dac

We live in a world in which the relevance for audio reproduction - ie what can a human really hear and what can they not - has little bearing on the engineering quest or the saleability of a product.
 

1 bit dac .v

After some thought I rejected my idea in (3) as sub-optimal and came up with a circuit which is a switched capacitor charge pump feeding a pulsed current into an op-amp I-V converter. The circuit is not unlike that used by Philips in their IEEE J. Solid State Circuits article by Naus & Dijkmans (SC22 Jpp 390-395, June 1987). This is likely a very similar arrangement to that they used in their old TDA1547 bitstream DAC chip.

In my circuit I have used only one charge transfer capacitor capacitor which is charged to +2.5V or -2.5V w.r.t. a 2.5V reference during the first half of the bitslot, and then discharged into the op-amp summing node during the second half of the bitslot. The switch arrangement is the standard 4-switch circuit used for stray-insensitive SC integrators and I am using SN74LVC1G66 switches. An LME49710 op-amp with + input referenced to +2.5V does the I-V and also provides a pole at 500kHz to reduce hf noise on the output.

I did a noise analysis on this circuit with the values I calculated and the results suggested I would have a noise floor around -120dBu.

When simulated on TINA spice the circuit behaved as expected, and better still, when I prototyped it on copper clad, it still behaved as expected. I haven't yet done performance tests - it's not wise to push the gods of electronics too far on one weekend!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top