ivlsi
Advanced Member level 3
Hello All,
What Timing Considerations should be taken into account for the Top-Level Synthesis with I/O ring?
Should the constraints be applied on the external pins of the I/O ring (pads)? How should they be calculated?
Thank you!
What Timing Considerations should be taken into account for the Top-Level Synthesis with I/O ring?
Should the constraints be applied on the external pins of the I/O ring (pads)? How should they be calculated?
Thank you!