Top-block layout clean in LVS calibre but not in Hercules...

[mask_layout]

hercules pin swappable

hi Guys,

Im running LVS verification in Hercules to get SPEF files for RC extraction. However, verification fails to complete top level compare due to equivalency errors. This layout is clean in calibre but we got no CCI liscense. What parameters can i toggle in hercules to fix my problems.

Please help.

 

[cdic]

layout clean

you sure logic is different? or just property error?

 

[mask_layout]

Re: Top-block layout clean in LVS calibre but not in Hercule

you sure logic is different? or just property error?

Im verifying thesame digital logic circuit GDS with the same Astro generated verilog netlist.

Im verifying the layout in Calibre and Hercules. Results in Calibre shows clean. In Hercules, All lower level cells get clean. But Top level says it has equivalence errors and failed to compare. It says possible port swap. Im thinking that im setting something wrong in hercules parameters but i dont know what it is

 

[cdic]

Re: Top-block layout clean in LVS calibre but not in Hercule

Oh, I see. Then it must because of the pin swap, there are some options you can set in both calibre and hercules to ignore it.

 

[vikaskm]

Re: Top-block layout clean in LVS calibre but not in Hercule

Hmm there are certain things you would want to look into when you are checking using hercules, it is a hierarchial tool , you would want to see if the pins you are propogating are the ones going from top to bottom are same, and if the layers that you might have drawn are on the same hierarchial level.