to wadaye (about asic design)

[fpga123]

pls give some answer!

Now i am take part in one prj about pci ip desgin.
i have finished the FPGA verification.
i am familiar with the FPGA design flow.
but i am going to start the ASIC desgin flow later.
so i want you to give me detail desgin flow.

i have read the book advaned chip synthesis,
and know first synthesis(dc) ->then DFT(insert scan)(dc)->then STA(pt)
->then ATPG(tmax)->the Formal check(lec)

it is only the front end part.

maybe the design flow is wrong, pls tell me. thx all.
where could i find the tut about it.

 

[wadaye]

Hi fpga123:

Basicly the flow is right, but we often do ATPG after layout, because

layout guys often reorder the scan-chain.

And I think Vendor's(TSMC/UMC) reference flow is good reference for

you.

 

[archer]

It just depends on the design flow of your design house. COT(Customer Owned Tools), ASIC etc.

 

[fpga123]

thx.

but where i could get what you said about?
i think i could do the synthesis with DC firstly.
but what is the synthesis target, max frequency timing or min area?

On FPGA i require the design to fit the device with suitable frequency and met the suitable constraints.
but on ASIC what is I could get?

maybe it is very difficult that i use the FPGA design flow to learn the ASIC design flow.
i want to get some answer from discussion.

 

[wadaye]

Hi fpga123:

You can find the reference flow of TSMC in this forum.

The timing/area require is from your chip's spec. I think you should

have a spec for your design.

 

[Arthurzss]

There is no simulation?
post-layout simulation is very important.

 

[fpga123]

yes. I know what you said.

thx you very much.

by the way, i think your photo is very funny.maybe
he is your idol.