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to prevent parasitic channel form

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020170

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I have a question while read "the art of analog layout" by written Hastings.

in CHAP 4, 138p, I saw this method to prevent parasitic p channel form in p MOSfet

author present the method figure B.

in my opinion, however, parasitic P channel become large through method B,

because there is too close distance between P+ diffusions

So I thought that the way of prevent parasitic P channel in Fig A is better than one

in Fig B, because the distance is too far between P+ diffusions

How about your thought?

thanks
 

sunking

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of course B is better.
there is no channel in B. In fact, it is short by the well.
do you notice the path between the gate and well?
 

rfsystem

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That is right! The channel is formed between psub and p+. The MOS device which connect psub and p+ together is the so called fieldoxide PMOS. If the gate voltage is negative enough it create short or leakage of the NWELL. In most processes the threshold voltage of the field oxide MOS is lower than the maximum allowed gate voltage of the other devices. But long before it create subthreshold current. That is the reason for that rule.
 

    020170

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