[SOLVED] TIQ comparator delay-time problem

[huy0189]

Hi,
I am struggling to get rid of the time-delay caused by inverter?
I am appreciate any help from you guys.
I really need to solve this problem ASAP.
Thanks

 

[dick_freebird]

You can't get rid of it, if you need inversion. Now you
might flip comparator inputs and lose one inverter stage
(presuming no other circuit downside, like loss of drive
and actually increasing net delay as a result).

More likely your comparator analog section, not some
inverter, is the bulk of the lag. That wants more current,
lower signal swings and more front end gain especially
in low-overdrive applications - and prevention of any
large-underdrive initial conditions from winding up the
gain lineup. Comparator speed being very dependent
on overdrive, especially in simple topologies.

 

[huy0189]

Thanks for replying Dick, but I am not sure that I totally understand.
The purpose of using this TIQ technique is to save as much power as possible since I have to design a 4bit Flash ADC.
The configuration of my circuit is to use Vdd of 1V and it uses 130nm technology.
for this comparator, I use 2 pairs of inverter. 1 for comparison, other is used to make the edge sharper.
Due to the delay time of these inverters, the distance between comparator outputs are not the same. Some are very close to each other. Others are very far.
How can I fix this error?