[SOLVED] Tips for layout needed on thermal behaviour

[alexxx]

Hello.

The below part is an H-bridge layout, 2 layers. FETs are SMD and use the printed board as cooler.




Now after some searching I thought that maybe there is a better way from thermal point of view, having less vias.




Adding thermal relief, it should look like that:




What do you think? Will thermal behaviour be improved?

Thanks,
Alexandros

 

[FvM]

FETs are SMD and use the printed board as cooler.

The first layout isn't bad. Thermal relief is a no-no for cooling purposes. You preferably would want to solder the board on a hot plate or in reflow oven, thus soldering of the transistor on the large copper pour isn't a problem. A solder mask should be provided, however.

Thermal relief is reasonable only for thru-plated component pads.

 

[alexxx]

A solder mask should be provided, however.

I have seen such a construction, which leaves the surface down of the FETs on the bottom layer without mask, leaving it as exposed metal. Not all the copper area, just the surface underneath FETs. Is this valid?

 

[FvM]

Yes, I've taken this as granted, the solder mask has an opening identical to the large FET pad. Thats the standard footprint, with or without a larger copper pour and/or thermal vias. You can also solder without a mask, but then the solder spreads over the copper pour.

 

[alexxx]

Thanks for the tips!

 

[marce]

FYI
Thermal Vias – A Packaging Engineer’s Best Friend « Electronics Cooling Magazine – Focused on Thermal Management, TIMs, Fans, Heat Sinks, CFD Software, LEDs/Lighting
http://www.gendreaumicrosystems.com/images/d2pak-thermal-vias.JPG
http://powerelectronics.com/mag/602PET22.pdf