Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Tinning Trace Requirement

Status
Not open for further replies.

tangy99

Newbie
Joined
Oct 6, 2020
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
14
What are some things that need to be considered when designing a PCB and with tinned traces? (i.e. spacing between other traces, thickness of trace, etc.). Is there a minimum spacing I should have between traces? How much of the trace should be exposed?
 

Hi,

What's the use of it?
Give your requirements.

Generally one just removes to solder stop in the PCB layout (tool).
Then the trace automatically gets tinned....like a pad.

If you ask about any production limits, then you need to talk with the manufacturer.

Klaus
 

Hi,

... with tinned traces?

How much of the trace should be exposed?

according to those questions it seems you are aiming to increase the current handling capability of your traces by adding additional soldering tin on top of your traces, if so this video might be of interest


BR
 

Specific resistance of tin is factor 8 to 10 higher than copper. If you don't manage a quite thick tin layer, the effect will be rather small.

We see tinned power traces in some consumer PCA, I wonder if the design is substantiated by actual calculation and measurements or if it's just superstition.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top